This paper describes a family of list-free tree-set scanning (LIFTS) algorithms, related to Shapiro's (1993) embedded zero-tree wavelet (EZW) coding and to Said and Pearlman's (see IEEE Trans. on Circuits and Systems for Video Technology, vol.6, no.3, p.243-9, 1996) set partitioning in hierarchical trees (SPIHT) algorithm. The principal advantage of the LIFTS algorithms is that they are parallelizable and require greatly reduced computational complexity and memory overhead, while nearly achieving the efficiency of SPIHT. The algorithms may be tailored to special requirements, such as transmission of a fully embedded bit-stream with sub-image refinement.

Achieving the potential performance of highly parallel MIMD processor architectures is critically dependent on both the speed and routing capabilities of the network fabric. The routing network of the AT&T DSP3 processor is described together with an indication of how the 40 megabyte/s links can be configured to meet diverse application requirements. Scaling to very large configurations is aided by compact packaging. Silicon-on-silicon multi-chip modules together with a novel three-dimensional vertical interconnection technology are being used to repackage the DSP3 into the ultra-dense processor.>

Describes a parallel computer architecture targeted at signal pattern analysis applications, scalable to configurations capable of TeraFLOP (10/sup 12/ floating point operations per second) throughput. An important attribute of the architecture is its low interconnection overhead, making it well suited to miniaturization using advanced packaging. Preliminary design and thermal tests project a computing density of 300 GigaFLOPS per cubit foot. The architecture is reconfigurable as a tree machine, one or more rings, or a set of linear systolic arrays. Fault tolerance is achieved by embedding these topologies within a four-connected lattice, growing around any faults. A performance model is derived and used to analyze the impact of skewness of the embedded trees on the execution time of parallel recognition algorithms.>

The architecture of the AT&T DSP-3 parallel processor is described. The DSP-3 design is modular and when implemented with 128 processing nodes, provides a maximum throughput of 3.2 GFLOPS (32 bit floating point). The high speed interconnection network (40 Mbytes/sec) contains redundant paths that allow the machine to be configured in a variety of topologies. This flexibility supports efficient operation for a diverse set of signal processing applications and enables topology reconfiguration in support of fault tolerance. Advanced multi-chip 3-D packaging will allow a 800 MFLOP version of the machine to be realized in a multi-processor array volume of 9 cubic inches.

The investigation of parallel computer architectures and parallel algorithms for speech recognition is important. Large vocabulary speech recognition is a computationally intensive problem, which can require orders of magnitude acceleration over a single processor to achieve real-time performance. Also, there is still much algorithm development work to be done, which requires a programmable computer rather than a fixed hardware implementation. This paper describes progress on the ASPEN parallel computer, that is applicable to signal understanding problems in general and large-vocabulary speech recognition in particular. The following will be described in this paper: the hardware architecture; the software architecture; classes of pattern recognition algorithms that are well-suited to the architecture; examples from speech recognition.

A high-speed Wallace-tree type combinational multiplier chip has been fabricated as a technology demonstration device using 1.5 μm NMOS processing. Multiply rates well in excess of 40 mHz have been obtained from laboratory devices. Extensive use of cascaded MOS transmission-gate (or steering) logic resulted in worthwhile improvements in power, average gate delay, and device topology.

The architecture of a programmable signal processor designed at Bell Laboratories is described.

The arithmetic unit of a digital computing element for a proposed globally controlled, highly parallel computer having up to thousands of such computing elements is described. Because operand words are regarded as circular, and any digit position may be designated as most significant during an operation, the atom of the computing element is the digit position logic, i.e., the computing elements are themselves composed of identical modules for each digit. The entire computing element, consisting of the arithmetic unit, an 8192 bit IGFET memory, and a special purpose input unit can be packaged on a 3.75 inch by 4.5-inch ceramic substrate using beam lead integrated circuits.

Abstract—A digital processor capable of computing the discrete Fourier transform for a range of audio signals in real time has been built as part of a facility to conduct research in signal processing. The digitized sample values can be complex. The arithmetic unit is configured to perform complex connectives, and automatic array scaling is used to make numerical accuracy independent of signal level. The Cooley–Tukey "fast Fourier transform" is the algorithm used.