This paper reports on a field programmable gate array (FPGA) implementation of Chaotic Boltzmann Machine Reservoir Computing (CBM-RC). The reservoir will be large-scale, as it is expected to be applied to sensor information prediction for autonomous mobile robots. Therefore, we employ a design premised on storing the weight information into a large memory outside the FPGA. We propose an efficient compression method for the weight matrix and a parallel processing system, by considering both the characteristics of CBM-RC and the fact that the weight matrix of a large-scale reservoir is generally a sparse matrix. Our RC system, which has more than 8000 neurons and 1024 inputs/outputs, has been implemented on an AMD Alveo U50 FPGA board. This RC is the largest scale compared to those in related studies. We have performed the NARMA10 task and demonstrated that we can estimate 1024 predictions at once with NMSE accuracy that is even or better to conventional RC.

While FPGAs are mainly used for implementing general purpose logic circuits, the RHW works with the CPU to accelerate the computation intensive part of the application by reconfiguring its data paths and ALUs optimized for the algorithm. Hence the RRW was designed to implement multi-bit data paths and ALUs efficiently. We developed a new architecture that consists of a two-dimensional array of multi-bit original ALU that is composed of a type of adder with multi-functional pre-logics.

This paper describes the GRD (Genetic Reconfiguration of DSPs) chip, which is evolvable hardware designed for neural network applications. The GRD chip is a building block for the configuration of a scalable neural network hardware system. Both the topology and the hidden layer node functions of a neural network mapped on the GRD chips are dynamically reconfigured using a genetic algorithm (GA). Thus, the most desirable network topology and choice of node functions (e.g., Gaussian or sigmoid function) for a given application can be determined adaptively. This approach is particularly suited to applications requiring the ability to cope with time-varying problems and real-time constraints. The GRD chip consists of a 100 MHz 32-bit RISC processor and 15 33 MHz 16-bit DSPs connected in a binary-tree network. The RISC processor is the NEC V830 which executes mainly the GA. According to chromosomes obtained by the GA, DSP functions and the interconnection among them are dynamically reconfigured. The GRD chip does not need a host machine for this reconfiguration. This is desirable for embedded systems in practical industrial applications. Simulation results on chaotic time series prediction are two orders of magnitude faster than on a Sun Ultra 2.

In contrast to conventional hardware where the structure is irreversibly fixed in the design process, evolvable hardware (EHW) is designed to adapt to changes in task requirements or changes in the environment, through its ability to reconfigure its own hardware structure dynamically and autonomously. This capacity for adaptation, achieved by employing efficient search algorithms based on the metaphor of evolution, has great potential for the development of innovative industrial applications. This paper introduces EHW chips and six applications currently being developed as part of MITI's Real-World Computing Project; an analog EHW chip for cellular phones, a clock-timing architecture for Giga hertz systems, a neural network EHW chip capable of autonomous reconfiguration, a data compression EHW chip for electrophotographic printers, and a gate-level EHW chip for use in prosthetic hands and robot navigation.

This paper describes reconfigurable massively parallel computer system called SOP (Sea Of Processors) that has ability to change its structure and achieves high performance by mapping the control flow and data flow of target algorithms directly on the reconfigurable hardware. SOP system consists of huge number of programmable logic, memory and switch elements. Each logic element is mainly used to map logic/arithmetic operations and control circuits. SOP memory element has ability to process global search, global sorting, heap tree and min/max operations quickly. SOP compiler extracts high degree of parallelism from application programs written in C-language by exploiting operation and function level parallelism using control-data-flow based mapping technique.