A D-band (114--170GHz) CMOS transceiver (TRX) chipset covering a 56GHz signal-chain bandwidth with a 640-Gb/s data rate is proposed in this work. The design includes an 8-way low-Q power-combined power amplifier (PA), a 2-way low-Q power-combined low noise amplifier (LNA), wideband-impedance-transformation mixers, and common-source-based cascaded distributed amplifiers (DA) to improve bandwidth and linearity. The proposed TRX chipset achieves a 200Gb/s SISO data rate and a 640Gb/s MIMO data rate.

A tri-mode mixer supporting the 5G NR standards over 24.25--71GHz is presented. The harmonic-selection technique reduces the local oscillator (LO) frequency range and power consumption. Besides, the proposed multiphase LO rejects unwanted harmonics. Fabricated in a 65nm CMOS process, this work consumes 12-21mW power under a 1V supply. It presents more than 20dB rejections to the undesired harmonic components at all operation bands. The required LO frequency range is only 10GHz.

An 8-Element 28-GHz time-division MIMO beamformer supporting 4x4 MIMO is presented. A fast-switching phase shifter is utilized to realize Nyquist-rate beam switching to lossless receive multiple beams by reuse single RF signal path. A prototype fabricated in 65nm CMOS achieves 64-QAM 4x4 MIMO reception in OTA measurement using four 5G NR spatial data streams with 400MHz channel bandwidth.

In this work, theoretical background of millimeter-wave/THz phased-array communication will be introduced as well as design challenges of THz transceiver by CMOS. Sub-THz transceivers realized by 65nm CMOS technology will be introduced. The paper concludes with a discussion on future directions of THz wireless communication, based on Shannon and Friis equations.

Cardio-vascular diseases (CVDs) are growing rapidly these days, which motivates to design an ultra-low power wearable cardiac monitor for early detection. In this work, we proposed an ultra-low power application-specific integrated circuit (ASIC) that can detect the P, R, and T peaks of the Electrocardiogram (ECG) signal. These peaks are useful for early detection of CVDs. The proposed design consists of a low-power analog front end followed by a peak-detection circuit, which can detect the P, R, and T peaks from an incoming single-lead differential ECG signal. The time-varying amplitude difference between the adjacent ECG peaks are efficiently detected by the proposed design. The proposed peak detector circuit has a self-adjustable discharge rate, which depends on the amplitude of the peak. The circuit is designed at the sub-threshold region to reduce the power consumption of the overall design. The proposed design extracts the digital output with the temporal information from the peaks of the ECG signal without using an analog-to-digital converter (ADC), one of the most power-hungry blocks in conventional biomedical signal acquisition architectures. A test chip has been fabricated in an industrial 0.18 µm CMOS process and occupies an active area of only 0.848 mm2. Measured results show that the proposed design consumes only 299.45 nW of power with a supply voltage of 0.9 V at typical operating conditions, which represents an improvement of 27.07%, 34.57%, and 51.93% over the existing state-of-the-art design. As it consumes ultra-low power, occupies less silicon area, and reliably extracts the ECG peaks, the proposed design is highly suitable for wearable healthcare applications.

This paper presents a tri-mode band-selection CMOS down-conversion mixer supporting the 5G NR standards over 24.25–71 GHz. The harmonic-selection technique reduces the required local oscillator (LO) frequency range and power consumption. The second-harmonic selection mode works for the 39-GHz and 47-GHz bands, while the fundamental-selected and third-harmonic selection modes operate for the 28-GHz and 60-GHz bands, respectively. Besides, in cooperation with the proposed multi-phase LO, the mixing components behave destructively for the undesired harmonics and constructively for the desired component, which shows the rejection of unwanted harmonics. Fabricated in a 65-nm CMOS process, this work presents flat conversion gain and more than 20-dB rejections to the undesired harmonic components at all operation bands. The required LO frequency range is only 10 GHz. Occupying a core area of 0.0077 mm2, the proposed mixer consumes power of 12-21 mW in three modes under a 1-V supply.

This work first discusses the future directions of millimeter-wave wireless communication, based on Shannon and Friis equations. Afterward, 28-GHz and 39-GHz phased-array transceivers realized by 65nm CMOS technology are introduced, which are designed for 5G and beyond. The 28GHz phased- array transceiver is designed based on a neutralized bi-directional technique. The required chip area for the element transceiver is reduced to half. A cross-pol. leakage canceller is also implemented along with the transceiver to suppress the crosspol. leakage. Therefore, the dual-polarized 28-GHz phased-array module is capable to improve the wireless data with dual- polarized MIMO (DP-MIMO) configuration even under severe polarization coupling and rotation conditions. The measured DP-MIMO EVMs are 3.4% in both 64-QAM and 256-QAM. The 8-element 39GHz phased-array transceiver is also designed based on the compact bi-directional architecture. The Doherty technique is utilized in TX mode to increase the power efficiency at power backoff region. A 64-element transmitter array realizes a saturated output EIRP of 55.2dBm. To improve the phased- array performance under digital pre-distortion (DPD), an inter- element mismatch compensation technique is further employed. By utilizing the proposed mismatch compensation, the measured 64-QAM OFDMA-mode EVM and ACLR with the shared-look- up-table (shared-LUT) DPD are improved from -22.4dB to - 25.0dB and from -28.7dBc to -32.1dBc, respectively.

A 300GHz CMOS-only wireless transceiver that achieves a maximum data rate of 34Gb/s while consuming a total power of 0.41W from a 1V supply is introduced. A subharmonic mixer with low conversion loss is proposed to compensate the absence of the RF amplifiers in TX and RX as a mixer-last-mixer-first topology is adopted. The TRX covers 19 IEEE802.15.3d channels (13-23, 39-43, 52-53, 59).

This paper presents high-accuracy phase and amplitude detection circuits for the calibration of 5G millimeter-wave phased array beamformer systems. The phase and amplitude detection circuits, which are implemented in a 65nm CMOS process, can realize phase and amplitude detections with RMS phase error of 0.17 degree and RMS gain error of 0.12 dB, respectively. The total power consumption of the circuits is 59mW.

An energy efficient digital polar transmitter (TX) based on 1.5bit Delta-Sigma modulator (DSM) and fractional-N injection-locked phase-locked loop (IL-PLL) is proposed. In the proposed TX, redundant charge and discharge of turned-off capacitors in the conventional switched-capacitor power amplifiers (SCPAs) are avoided, which drastically improves the efficiency at power back-off. In the PLL, spur-mitigation technique is proposed to reduce the frequency mismatch between the oscillator and the reference. The transmitter, implemented in 65nm CMOS, achieves a PAE of 29% at an EVM of -25.1dB, and a system efficiency of 23.8%.

A phase shifter with temperature compensation for 28GHz phased-array TRX is presented. A precise low-voltage current reference is proposed for the IDAC biasing circuit. The total gain variation for a single TX path including phase shifter and post stage amplifiers over -40°C to 80°C is only 1dB in measurement and the overall phase error due to temperature is less than 1 degree without off-chip calibration.

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-Nmultiplying delay-locked loop(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets (SPO) between bang-bang phase detector (BBPD) and multiplexer (MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets (DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48ps root-mean-square (RMS) jitter in fractional-N and integer-N modes, respectively. The fractional spur is less than -59.0dBc, and the reference spur is -64.5dBc. The power consumptions are 1.85mW and 1.22mW, corresponding to figures of merit (FOM) of -240.4dB and -245.5dB.

This article presents a small-area Bluetooth Low-Energy (BLE) transceiver (TRX) for short-range Internet-of-Things (IoT) applications in 65-nm CMOS. An integrated Radio-Frequency Input-Output (RFIO) circuitry embedded with transmitter/receiver (TX/RX) switch function and on-chip impedance matching is proposed. A hybrid-loop TRX structure based on a wide-bandwidth fractional-N digital phase-locked loop (DPLL) is implemented to achieve the maximum power reduction. A -94dBm receiver sensitivity is achieved with 2.3mW receiver power consumption, while a RF receiving bypass route integration enhances the input power tolerance. The BLE transceiver delivers -6dBm output power while consuming 2.6mW and delivers 0dBm output power while achieving 18.5% maximum TX efficiency. Thanks to the RFIO with harmonic suppression, -56dBc of 2nd-order harmonic distortion (HD2) and -48dBc of 3rd-order harmonic distortion (HD3) suppression are achieved with 0.85mm2on-chip area. This transceiver satisfied the BLE radio specification without the need for external filters and with low-power consumption, which enables minimum size and long life-time modules.

A 28GHz differential bi-directional amplifier in a standard 65nm CMOS process is presented. This work is realized based on the neutralized bi-directional core together with the fully shared inter-stage matching networks. The core chip area is only 0.11mm2. At 28GHz, a 15.1-dBm saturation output power and a 4.2-dB noise Figure are realized for PA mode and LNA mode, respectively. The DC power consumptions for PA mode and LNA mode are 149mW and 31mW, respectively, under 1-V DC supply.

In this paper, a way to realize 1Tbps in wireless will be discussed based on Shannon and Friis equations. Several millimeter-wave CMOS transceivers will be also introduced to show possible ways to realize more than 100Gb/s data rate by using the present circuit and device technology. The importance of active and passive device characterization is provided and examples are given with relevant references.

A W-band ultra-high data-rate (56Gb/s) wideband (68-102GHz) 65nm bulk CMOS wireless transceiver is presented. Frequency interleaving by two up-converted IF data signals using 68 and 102GHz LO to W-band is applied to achieve wideband and a world-record 56Gb/s wireless communications on CMOS. 16QAM modulation is used for 6.5GHz (26Gb/s) low-band and 7.5GHz (30Gb/s) high-band data. Transmitter/receiver (TX/RX) consumes 260/300mW from 1V DC supply.

This paper presents an HDL-synthesized injection-locked phase-locked loop using LC-based DCO for on-chip clock generation. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm CMOS process, this prototype demonstrates a 0.142ps integrated jitter at 3.0GHz and consumes 4.6mW while only occupying an area of 0.12mm2. It achieves a figure of merit (FoM) of -250.3dB, which is the best for the synthesized PLL up-to-date.

This paper proposes a noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. The phase interpolator helps reduce the jitter introduced into the system by the multi-phase generation mechanism used for the fractional operation. The proposed frequency synthesizer is fabricated in 65nm CMOS process and it is capable of working at frequencies ranging from 4.3GHz to 4.9GHz. The measured close-in phase noise is −113dBc/Hz at an offset of 200kHz from the carrier with 3.3mW power consumption, which results in a FoM of −246dB.

This paper presents an automatic place-and-routed two-stage fractional-N injection-locked PLL (IL-PLL) using soft injection technique for on-chip clock generation. Fabricated in a 65nm CMOS process, this prototype demonstrates a 3.6-ps integrated jitter at 1.5222 GHz and consumes 3mW leading to an FoM of -224.6 dB while only occupying an area of 0.048 mm2. It realizes the first fully synthesized fractional-N injection-locked PLL up-to-date.

This paper proposes a tail-current modulated VCO with adaptive-bias scheme. The proposed adaptive-bias scheme ensures robust startup conditions for the tail-feedback VCO. A tail-feedback VCO using the proposed scheme is implemented in a 0.18-μm CMOS process. The measured phase noise is -119.3dBc/Hz at 1MHz offset with a power dissipation of 6.8mW at 4.6GHz.

This paper presents a low power and low noise sub-harmonically injection-locked PLL using a 20GHz sub-sampling PLL (SS-PLL) and a quadrature injection locked oscillator (QILO). Lower in-band phase noise and out-of-band phase noise have been achieved through the sub-sampling phase detection and sub-harmonic injection techniques, respectively. Implemented in a 65nm CMOS, this work can support all 60GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset while consuming 20.2mW and 14mW from the 20GHz SS-PLL and the QILO, respectively.

This paper presents a small area, low power, fully synthesizable PLL with a current output DAC and an interpolative-phase coupled oscillator using edge injection technique for on-chip clock generation. A prototype PLL is fabricated in a 65nm digital CMOS process, achieves a 1.7-ps integrated jitter at 0.9 GHz and consumes 0.78 mW leading to an FOM of -236.5 dB while only occupying an area of 0.0066 mm2. It achieves the best performance-area trade-off.

This paper presents a compact, low power, and low jitter dual-loop injection-locked PLL with synthesizable all-digital background calibration system for clock generation. Implemented in a 65nm CMOS process, this work demonstrates a 0.7-ps RMS jitter at 1.2 GHz while having 0.97-mW power consumption resulting in an FOM of -243dB. It also consumes an area of only 0.022mm2resulting in the best performance-area trade-off system presented up-to-date.

A swing-enhanced current-reuse class-C VCO which can theoretically achieve same phase noise figure-of-merit (FoM) as other class-C VCOs at the lowest power consumption is presented. A swing enhancement in class-C operation and an oscillation robustness are achieved through dynamic bias control circuits for both NMOS and PMOS transistors. The proposed VCO has been fabricated in 180nm CMOS process while oscillating at 4.6 GHz. The measured phase noise is -119 dBc/Hz at 1 MHz offset while consuming 1.6 mA from 1.5 V supply. An FoM of -189 dBc/Hz is achieved.

This paper presents an area-efficient frequency synthesizer with a quadrature phase output using a fractional-N injection-locking technique for software-defined radios. A background calibration scheme is proposed to compensate for the PVT variations. Implemented in a 65nm CMOS process, this work demonstrates 10 MHz to 6.6 GHz continuous quadrature frequency coverage, while only occupies a small area of 0.38 mm2and consumes 16-26 mW depending on output frequency, from a 1.2 V power supply. The normalized phase noise achieves -135.3 dBc/Hz at 3 MHz offset, and -95.1 dBc/Hz in-band phase noise at 10 kHz offset, from a 1.7 GHz carrier frequency.

This paper presents a 60-GHz direct-conversion transceiver in 65 nm CMOS technology. By the proposed gain peaking technique, this transceiver realizes good gain flatness and is capable of more than 7 Gbps in 16QAM wireless communication for all channels of IEEE802.11ad standard within EVM of around -23 dB. The transceiver consumes 319mWin transmitting and 223mW in receiving, including the PLL consumption.

A 58.1-to-65.0 GHz frequency synthesizer using sub-harmonic injection-locking technique is presented. The synthesizer can generate all 60GHz channels defined by IEEE 802.15.3c, wirelessHD, IEEE 802.11ad, WiGig, and ECMA-387. A frequency calibration scheme is proposed to monitor frequency shift resulting from environmental variations. Implemented in a 65nm CMOS process, the synthesizer achieves a typical phase noise of -117 dBc/Hz @10MHz offset from a carrier frequency of 61.56 GHz.

This paper presents a feedback class-C VCO with PVT-robustness and enhanced oscillation swing. The proposed VCO starts oscillation as a differential LC-VCO for robust startup, and automatically adapts to an amplitude-enhanced class-C VCO in steady-state for lower phase noise. The proposed VCO is implemented in a 0.18μm CMOS process. The measured phase noise at room temperature is -125 dBc/Hz @ 1MHz offset with a power dissipation of 3.4-mW, from a carrier frequency of 4.84-GHz. The figure-of-merit is -193 dBc/Hz.

This paper presents a 60-GHz direct-conversion transceiver using 60-GHz quadrature oscillators. The 65 nm CMOS transceiver realizes the IEEE802.15.3c full-rate wireless communication for every 16QAM/8PSK/QPSK/BPSK mode. The maximum data rates with an antenna built in a package are 8 Gbps in QPSK mode and 11 Gbps in 16QAM mode within a BER of-3. The transceiver consumes 186 mW while transmitting, and 106 mW while receiving. The PLL also consumes 66 mW.

This paper proposes Progressive Mixing Injection Locked Frequency Divider (PMILFD) technique that enhances the locking range for higher division ratios. As this technique uses lower and much stronger harmonics in the mixing process, it results in a stronger injection effect and a much wider locking range. Two 20GHz PMILFDs were designed based on this approach to divide by 4 and 8 using a 65nm CMOS process. The former achieves a 7.9GHz(31.4%) locking range and the later achieves a 3.4GHz(15.5%) while consuming 3.9mW and 7.1mW, respectively.

This paper proposes a 0.5-V LC-VCO with a frequency extension circuit to replace ring oscillators for ultra-low-voltage sub-1ps-jitter clock generation. Significant performances, in terms of 0.6-ps jitter, 50MHz-to-6.4GHz frequency tuning range with 2 bands and sub-1mW PDC, indicates the successful replacement of ring VCO for the future 0.5-V LSIs and power aware LSIs.

This paper proposes a 60GHz quadrature PLL frequency synthesizer that has a tuning range capable of covering the whole band specified by the IEEE802.15.3c with exceptional phase noise. The synthesizer is constructed using a 20GHz PLL that is coupled with a frequency tripler to generate the 60GHz signal. Both the 20GHz PLL and the ILO were fabricated using a 65nm CMOS process and measurement results show a phase noise of -96dBc/Hz at 60GHz while consuming 77.5mW from a 1.2V supply.

A tunable power amplifier (PA) from 2.1 GHz to 6.0 GHz is presented for multi-standard radios. The proposed multi-band PA can tune the output impedance to 50 ¿ over a wide frequency range, so external isolators following PAs can be eliminated. The PA is implemented by using a 0.18 ¿m CMOS process, and the supply voltage is 3.3 V. Over all of the frequency range, the PA realizes output return loss S22of smaller than -8 dB, power gain of larger than 12 dB, output 1-dB compression point of larger than 15 dBm.

This paper presents a 60 GHz direct-conversion transmitter in 65 nm CMOS technology. The power amplifier consists of 4-stage transistors. The circuit model of de-coupling capacitor is built as a transmission line to consider the physical length. In the measurement results, the conversion gain is above 9.6dB at 58–65GHz band, and the 1 dB compression point is 1.6 dBm with 60 GHz LO frequency and 1 dB LO power.

This paper demonstrates a low voltage differential signaling (LVDS)-type on-chip transmission line (TL) interconnect to solve delay issues on global interconnects. The proposed on-chip TL interconnect can achieve 10.5 Gbps signaling and has smaller delay, smaller delay variation and better power efficiency than conventional on-chip interconnects at high-frequencies.

This paper proposes a novel direct sampling mixer (DSM) using Switched Capacitor Filter (SCF) for multi-band receivers. The proposed DSM has a higher gain, more flexibility and lower flicker noise than that of conventional circuits. The mixer for Digital Terrestrial Television (ISDB-T) 1-segment was fabricated in a 0.18 μm CMOS process, and measured results are presented for a sampling frequency of 800 MHz. The experimental results exhibit 430 kHz signal bandwith with 27.3 dB attenuation of adjacent interferer assuming at 3 MHz offset.

This paper presents a novel small-area distributed mixer for ultrawide-band (UWB) receivers. The proposed mixer uses five 4-port inductors instead of fifteen 2-port inductors to shrink area of the circuit. The proposed mixer achieves conversion gain of -10 dB, noise figure of 15 dB, return loss of less than -10 dB from 2.3 to 6.0 GHz, IIP3 of 13.6 dBm, and the circuit area of 0.51 mm2.

This paper proposes a multiple-divide technique using by-2, by-3, and by-4 frequency dividers to realize a lower phase-noise LC-VCO, and explores the design space of low-phase-noise VCO using the multiple-divide technique. In the simulated results using 90-nm CMOS model parameters, the optimum frequency range, achieving better than −191 dBc/Hz of FoM, can be extended from 6–12 GHz to 1.5–12 GHz.

This paper proposes a self compensation technique. For LNAs, large power gain and large input signal results in too large output signal and distortion. To make matters worse, input power varies by process variation, temperature, simulation error, and so on. To solve the problem, the proposed LNA is equipped with variable bias circuit and can be reconfigured by bias voltage of transistors. It contributes to power reduction, compensation of intermodulation. The proposed LNA achieves more than 33 dBm in DeltaIM3, if the input power increases more than -30 dBm. Moreover the output power is less than about -12 dBm, which is 87 % of power reduction.

This paper proposes a wide-range tunable CMOS voltage controlled oscillator (VCO). VCO uses an on-chip variable inductor and switched capacitors as variable elements. The VCO was fabricated using a standard 0.18 mum CMOS process with five metal layers. The oscillation frequency can be tuned from 1.28 GHz to 2.75 GHz with tuning range of 72 %.

This paper proposes a branching method for on-chip transmission line (TL) interconnects, which can reduce delay and power of global interconnects. A 6-mm-long TL interconnect with a branch is fabricated by using a 0.18 mum standard Si CMOS process, and the measurement result performs 4Gbps signal transmission.

This paper proposes a reconfigurable low noise amplifier (LNA). The proposed LNA equips variable bias circuit and can be reconfigured by bias voltage of transistors. It contributes to power reduction, compensation of intermodulation, and output signal to noise ratio (SNR/sub out/). The proposed LNA achieves 73 % of power reduction by controlling bias voltage, and dynamic compensation of /spl Delta/IM3 and SNR/sub out/ is realized.

On-chip transmission-line interconnect has been proposed to reduce delay time and power consumption. The transmission line is used to replace long RC interconnects. This paper proposes the methodology to replace RC lines with transmission lines, which are estimated with Wire Length Distribution (WLD). Advantages of on-chip transmission line are discussed from the view point of delay time and power consumption.

This paper proposes a dynamic reconfigurable architecture for analog RF circuits. The architecture consists of RF circuits and a control circuit. The RF circuits can be reconfigured by bias voltages of transistors and variable passive components, and the RF circuit block can also be switched dynamically. The proposed architecture can realize the multi-band/mode RF circuit in single chip for the Software Defined Radio, which achieves considerable reduction of circuit area and power consumption. On the other hand, we can obtain robust RF circuits by the dynamic reconfiguration for the process variation, the dynamic change of temperature, etc.

Interconnect length distribution (ILD) represents a correlation between the number of interconnects and length. The ILD can predict power consumption, clock frequency, chip size, etc. It has been said that high core utilization and small circuit area improve chip performance. We propose a ILD model to predict a correlation between core utilization and chip performance. The proposed model predicts influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decrease of load capacitance is more important than that of total interconnect length for improvement of chip performance. The proposed ILD model expresses actual ILD more accurate than conventional models.

This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. Our model consists of a statistical transistor model and a gate-delay model. We present a modeling and extracting method of transistor characteristics for the intra-chip variability and the inter-chip variability. In the modeling of the intra-chip variability, it is important to consider a gate-size dependence by which the amount of intra-chip variation is affected. This effect is not captured in a statistical delay analysis reported so far. Our gate-delay model characterizes a statistical gate delay variation using a response surface method (RSM) according to the intra-chip and inter-chip variability of each transistor in a gate. We evaluate the accuracy of our model, and we show some simulated results of a circuit delay variation characterized by the measured variances of transistor currents.

The fluctuations of device characteristics are usually regarded as a normal distribution. However, if we consider the fluctuation over the whole wafer, the fluctuation cannot be expressed as a normal distribution due to the existence of a systematic component. We propose a model, characterizing the systematic component according to the distance from the center die, which can express the fluctuation over the whole wafer statistically.