Large-scale integrated (LSI) memory circuit reliability is reviewed. Reliability of large-scale integrated memory circuits is discussed. The major physical mechanisms for failures in memory LSIs and measures to counter these failures are reviewed. Fault-tolerant techniques, divided into the spare row/column line substitution. (SLS) technique and the on-chip error-correcting code (ECC) technique, developed to overcome hard and soft failures are described. Design approaches for realizing high performance and high reliability are also discussed.>

A standard form is presented for describing device characteristics in VLSI's. It serves as a standard interchange form for device characteristics between various design tools for VLSI's. The form is designed such that any relevant characteristic as a circuit component can be described. It also makes it possible to process an enormous amount of device data efficiently. A newly developed CAD system, which integrates device and circuit simulators, is also presented as a standard form application example. Any device simulator, which has outputs in the standard form, can be implemented into the system. By using the standard form, various device simulators are able to be used in total LSI design systems, which makes it possible to execute accurate simulations and designs for LSI using recent fine pattern technologies.

A novel three-dimensional (3-D) wiring capacitance simulator for VLSI circuits has been developed and successfully used in various applications, including DRAM-design. The simulator, TRICEPS, determines fully automatically 3-D total and coupling capacitances from mask and processing information. A novel simple input format, versatility, fast calculation time, and no need for any user interference make it a useful interactive development tool for dense VLSI circuits.