Demo Data from EDBT 2026 / reviewers in the wild / expert
Victor A. Chang
dblp:45/2737
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1999
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › parasitic extraction
interconnect capacitance extraction |
0.0 | 1 | 1999 | Exterior templates for capacitance computations [interconnections] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 |
Electronic design automation › physical design
parasitic extraction |
0.0 | 1 | 1999 | Exterior templates for capacitance computations [interconnections] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 |
Electronic design automation
physical design |
0.0 | 1 | 1999 | Exterior templates for capacitance computations [interconnections] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 |
Methods — techniques the papers use, named apart from their topics
infinite grid theory · 0.0exterior template · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1999 | Exterior templates for capacitance computations [interconnections]abstractThe computation of the capacitance coefficients for alternative interconnect configurations requiring repeated calculations as the configurations are changed can be substantially accelerated by using an "exterior template", that is, a set of "template capacitors" connected to the surface of the smallest rectangular region encompassing the planned interconnects. These template capacitors represent the effect of the medium for the fringing field outside the rectangle, and they eliminate the need to sample the fringing field every time a new calculation is made. The template capacitors can be determined by using the theory of infinite grids to eliminate almost entirely the medium-truncation error. All this works for both two-dimensional and three-dimensional (3-D) configurations, and it is especially advantageous in the 3-D case. Armen H. Zemanian, Victor A. Chang |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |