In addition to the conventional ADC design tradeoffs between power, speed, and accuracy, radiation tolerance is the fourth factor for ADCs used in radiation environments. This paper describes radiation-tolerant (RT) ADC design tradeoffs and design strategies. Then, the paper introduces a 13-bit RT pipelined-successive-approximation register (pipelined-SAR) ADC fabricated in 65 nm CMOS technology based on the concluded tradeoffs. To further improve the ADC power efficiency, a semi-time-interleaved (Semi-TI) structure is employed. Besides, the ping-pong auto-zeroing (AZ) scheme is implemented in the residue amplifier (RA) to reduce the TID-induced offset while maintaining low power dissipation. The proposed ADC is designed and hardened against Single Event Effects (SEEs) and Total Ionizing Dose (TID) effects from the structure to layout levels. All sub-blocks were examined, and only the critical blocks were hardened to avoid over-hardening. From the measurement results, the prototype ADC attains an 80 MS/s sampling rate and achieves 70.8-dB SNDR and 80.3-dB SFDR at the Nyquist input frequency. With a total power consumption of 13.8 mW, the prototype ADC establishes a state-of-the-art Walden Figure of Merit of 60.7 fJ/conv step, yielding an efficiency comparable to non-RT ADCs with similar specifications. Irradiation tests validate the consistent performance of the ADC up to a cumulative dose of 500 krad (Si) in X-ray testing, while laser testing indicates a robust SEE threshold and swift post-SEE recovery.

This work presents a capacitance-to-digital converter (CDC) fully designed using time-domain circuits following the principle of a dual quantization based first-order ΔΣ modulator. The prototype supports capacitance measurement within the range of 0-3.75 pF and is implemented using a 65-nm CMOS Technology. It consumes 2 mW from a 1.2 V supply while sampling at a 100 MHz clock frequency. The CDC prototype achieves an ENOB of 12.9 bits with an energy efficiency of 0.18 pJ energy per conversion-step.

Telehealth systems and applications are extensively investigated nowadays to enhance the quality-of-care and, in particular, to detect emergency situations and to monitor the well-being of elderly people, allowing them to stay at home independently as long as possible. In this paper, an embedded telehealth system for continuous, automatic, and remote monitoring of real-time fall emergencies is presented and discussed. The system, consisting of a radar sensor and base station, represents a cost-effective and efficient healthcare solution. The implementation of the fall detection data processing technique, based on the least-square support vector machines, through a digital signal processor and the management of the communication between radar sensor and base station are detailed. Experimental tests, for a total of 65 mimicked fall incidents, recorded with 16 human subjects (14 men and two women) that have been monitored for 320 min, have been used to validate the proposed system under real circumstances. The subjects' weight is between 55 and 90 kg with heights between 1.65 and 1.82 m, while their age is between 25 and 39 years. The experimental results have shown a sensitivity to detect the fall events in real time of 100% without reporting false positives. The tests have been performed in an area where the radar's operation was not limited by practical situations, namely, signal power, coverage of the antennas, and presence of obstacles between the subject and the antennas.

This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice level optimizations of simple building blocks and a full architecture optimization of the whole based on accurate models of the building blocks. The models of the building blocks are interpolated over the data points acquired in the Spice level simulations. The optimizer technique has been applied to the optimization of an architecture for a GPS receiver. The optimal design has been implemented in a standard 0.25μm CMOS process.