In order to achieve ultra-low power (ULP), ICs are being designed for VDD≤ 0.5 V. At these low voltages, random dopant fluctuations (RDFs) result in a stochastic component of logic delay that can be comparable to the global corner delay. Moreover, the probability density function (PDF) of this stochastic delay can be highly non-Gaussian. In order to predict the statistical impact of RDF-induced local variations on logic timing, it is necessary to incorporate these effects into a timing closure methodology. This paper presents a computationally efficient methodology for stochastic characterization of standard cell li- braries at low voltage, where the cell delay is a nonlinear function of the transistor random variables (RVs), and the resulting cell delay has a non-Gaussian PDF. It also presents a computation- ally efficient methodology for computing any point on the PDF of a timing path (TP) delay, in the case where cell delays are non-Gaussian. The method is called nonlinear operating point analysis of local variation (NLOPALV). The general NLOPALV theory is developed. It is applied to cell library characterization, and the accuracy of the NLOPALV approach is validated by comparison to Monte Carlo simulation. NLOPALV is also applied to timing path analysis on a 28 nm DSP IC. The approach has been implemented using commercial CAD tools, and integrated into a commercial IC design flow. The NLOPALV approach gives timing results that are within 5% accuracy compared to Monte Carlo analysis at VDD= 0.5 V. This compares to errors on the order of 50% when the Gaussian approximation is used.

For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ¿ 0.5 V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. This paper presents a computationally efficient algorithm for computing the PDF of logic Timing Path (TP) delay, which results from local variations. This approach is called Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach is implemented using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a 28 nm commercial DSP are analyzed using the proposed technique and the performance is observed to be within 5% accuracy compared to SPICE based Monte-Carlo analysis.

In the last couple of decades, handheld wireless devices such as cell phones have become one of the most prolific electronic devices in history. With this has come an exploding demand for performance and features that cover almost every aspect of our digital multimedia interconnected lives including 3-D gaming, still and video cameras, WAN, Bluetooth, high-speed data connections, and so on. As ever increasing features continue to be integrated into these products, there is an ongoing need to develop innovative ways to reduce power consumption and extend battery life. Only through continual process and circuit cooptimization are we able to reap the benefits of technology scaling required to meet the feature and performance demands in the face of increasing process variations and exponentially increasing leakage currents. As a result, SmartReflex power and performance technologies have been developed and applied to 90 nm, 65 nm, and 45 nm system-on-chip (SoC), to achieve optimal power and performance. SmartReflex technologies consist of two major components to optimize SoC power and performance: static and dynamic techniques. Static techniques like power-gating, retention and off-mode are used to lower leakage and allow for extended battery lifetimes for standby times. Dynamic techniques such as dynamic power switching, adaptive voltage scaling, dynamic voltage/frequency scaling with split-rail memories, and adaptive body-biasing address active power and performance challenges. These techniques enable SoC solutions with the performance of the latest process technology and provide the user with advanced multimedia features with orders of magnitude of power reduction.

In this paper, we identify the key challenges that oppose sub-threshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges.

This tutorial paper examines architectural and circuit design techniques for a microsensor node operating at power levels low enough to enable the use of an energy harvesting source. These requirements place demands on all levels of the design. We propose architecture for achieving the required ultra-low energy operation and discuss the circuit techniques necessary to implement the system. Dedicated hardware implementations improve the efficiency for specific functionality, and modular partitioning permits fine-grained optimization and power-gating. We describe modeling and operating at the minimum energy point in the subthreshold region for digital circuits. We also examine approaches for improving the energy efficiency of analog components like the transmitter and the ADC. A microsensor node using the techniques we describe can function in an energy-harvesting scenario.

Energy-aware design is highly desirable for systems that encounter a wide diversity of operating scenarios. This is in contrast to traditional low power design for the worst case scenario, which may not be globally energy efficient. Energy-aware design focuses on enabling architectures which scale down energy as quality requirements are relaxed. A new energy-scalable system design methodology is proposed for a Real-Valued FFT processor which supports variable bit precision (8 and 16-bit precision) and variable FFT length (128- 512 point). Two energy-aware architectures, Ensemble of Point Solutions method and Reuse of Point Solutions method, are described and evaluated. Simulated and measured results show a 66% energy savings for 8-bit datapath and 52% savings for 128-point FFT length over a non-scalable approach.

We introduce the notion of energy-scalable system-design. The principal idea is to maximize computational quality for a given energy constraint at all levels of the system hierarchy. The desirable energy-quality (E-Q) characteristics of systems are discussed. E-Q behavior of algorithms is considered and transforms that significantly improve scalability are analyzed using three distinct categories of commonly used signal-processing algorithms on the StrongARM SA-1100 processor as examples (viz., filtering, frequency domain transforms and classification). Scalability hooks in hardware are analyzed using similar examples on the Pentium III processor and a scalable programming methodology is proposed. Design techniques for true energy scalable hardware are also demonstrated using filtering as an example.

A scheme for efficient system partitioning of computation in wireless sensor networks is presented. Local computation of the sensor data in wireless networks can be highly energy-efficient, because redundant communication costs can be reduced. It is important to develop energy-efficient signal processing algorithms to be run at the sensor nodes. This paper presents a technique to optimize system energy by parallelizing computation through the network and by exploiting underlying hooks for power management. By parallelizing computation, the voltage supply level and clock frequency of the nodes can be lowered, which reduces energy dissipation. A 60% energy reduction for a sensor application of source localization is demonstrated. The results are generalized for finding optimal voltage and frequency operating points that lead to minimum system energy dissipation.

The potential for collaborative, robust networks of microsensors has attracted a great deal of research attention. For the most part, this is due to the compelling applications that will be enabled once wireless microsensor networks are in place; location-sensing, environmental sensing, medical monitoring and similar applications are all gaining interest. However, wireless microsensor networks pose numerous design challenges. For applications requiring longterm, robust sensing, such as military reconnaissance, one important challenge is to design sensor networks that have long system lifetimes. This challenge is especially difficult due to the energyconstrained nature of the devices. In order to design networks that have extremely long lifetimes, we propose a physical layer driven approach to designing protocols and algorithms. We first present a hardware model for our wireless sensor node and then introduce the design of physical layer aware protocols, algorithms, and applications that minimize energy consumption of the system. Our approach prescribes methods that can be used at all levels of the hierarchy to take advantage of the underlying hardware. We also show how to reduce energy consumption of non-ideal hardware through physical layer aware algorithms and protocols. 1

This paper present results from a wideband-CDMA downlink receiver implementation on the newly developed low-power Texas Instruments TMS320C55x DSP for wireless applications. The C55x includes new instructions and functional units, such as the dual multiply-accumulates (DualMAC), implicit/explicit parallelism, and an added pipeline stage. It also includes hardware in the address unit exclusively for memory address computation. This new architecture is suitable for implementation of systems that have large computational tasks and low-power requirements, such as baseband processing in the W-CDMA downlink receiver. The chip dissipates 0.25 mW/MIPS which is lower than the power dissipated in the current low power DSP, the C54x. We show that the C55x has a 40-60% improvement over the C54x in cycle efficiency in our implementation of a W-CDMA receiver.

Wireless microsensor networks lend themselves to trade-offs in energy and quality. In these networks, the individual sensor data per se are not necessarily important to the end user. Rather, it is the combined knowledge of all the sensors that describes what is occurring in the environment. By allowing the algorithms and protocols to adapt the quality of this description, with a corresponding change in energy dissipation, sensor networks can be flexible to the end-user's requirements. In this paper, we provide models for predicting quality and energy and show the advantages of trading off these two parameters. By ensuring that the system operates at a minimum energy for each quality point, the system can achieve both flexibility and energy efficiency, allowing the end-user to maximize system lifetime.

We introduce the notion of energy scalable computation on general purpose processors. The principle idea is to maximize computational qualityfor a given energy constraint. Teh desirable energy-quality behavior of algorithms is discussed. subsequently the energy-quality scalability of three distinct categories of commonly used signal processing algorithms (viz. filtering, frequency domain transforms and classification) are analyzed on the StrongARM SA-1100 processor and transformations are described which obtain significant improvements in the energy-quality scalability of the algorithm.