Jermy C. Smith

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3ranked-venue papers

2as first author

0since 2021 · last 1995

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorTheory of computation · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Hardware accelerators and domain-specific architectures · 46% Integrated circuit design · 46% Hardware reliability and fault tolerance · 7%

Topics — the 5 heaviest of 5, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Integrated circuit design digital circuit design	1	1995	A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications · IEEE Trans. Computers 1995
Hardware accelerators and domain-specific architectures › systolic array linear systolic array	1	1995	A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications · IEEE Trans. Computers 1995
Integrated circuit design › residue number system arithmetic residue number system processor	1	1995	A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications · IEEE Trans. Computers 1995
Hardware accelerators and domain-specific architectures systolic array	1	1995	A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications · IEEE Trans. Computers 1995
Hardware reliability and fault tolerance › fault-tolerant architecture fault-tolerant processor	1	1995	A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications · IEEE Trans. Computers 1995

Year	Publication	Venue	Position
1995	A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications abstract The design of a Galois enhanced quadratic residue number system (GEQRNS) processor is presented, which can be used to construct linear systolic arrays. The processor architecture has been optimized to perform multiply-accumulate type operations on complex operands. The properties of finite fields have been exploited to perform this complex multiplication in a manner which results in greatly reduced hardware complexity. The processor is also shown to have a high degree of tolerance to manufacturing defects and faults which can occur during operation. The combination of these two factors makes this an ideal candidate for array signal processing applications, where high complex arithmetic data rates are required. A prototype processing element has been fabricated in 1.5 /spl mu/m CMOS technology, which is shown to operate at 40 MHz.> Jermy C. Smith, Fred J. Taylor	IEEE Trans. Computers	1
1994	The design of a fault tolerant GEQRNS processing element for linear systolic array DSP applications abstract In this work the design of a Galois Enhanced Quadratic Residue Number System processor is presented, which can be used to construct linear systolic arrays. The processor architecture has been, optimized to perform multiply-accumulate type operations on complex operands. The processor is also shown to have a high degree of tolerance to manufacturing defects and faults which occur during operation. A prototype integrated circuit has been fabricated in 1.5 /spl mu/m CMOS technology, which is shown to operate at 40 MHz.> Jermy C. Smith, Fred J. Taylor	Great Lakes Symposium on VLSI	1
1993	The Gauss machine: A Galois-enhanced quadratic residue number system systolic array abstract The Gauss machine is a SIMD systolic array architecture that takes advantage of the Galois-enhanced residue number system (GEQRNS) to form reduced-complexity arithmetic elements. The Gauss machine is targeted at front-end signal and image processing applications. A discrete prototype that achieves a peak rating of 320 million complex arithmetic operations per second while operating at 10 MHz has been constructed. A VLSI implementation of the Gauss machine's processor cell has been created. The VLSI implementation is implemented in 2.0-/spl mu/m CMOS and achieves greater than 20-MHz performance, using less than 2.0-mm/sup 2/ die area. It is shown that techniques for defect tolerance in RNS systolic arrays can result in substantial yield enhancement, thereby making larger than conventional (ULSI) systems possible.> Jonathon David Mellott, Jermy C. Smith, Fred J. Taylor	IEEE Symposium on Computer Arithmetic	2