The data exchange between GPGPUs and CPUs are becoming more and more important nowadays. One trend in industry to alleviate the long latency is to integrate CPUs and GPGPUs on a single chip. In this paper, we analyze the reference interactions between CPU and GPGPU applications with a CPU-GPGPU co-simulator that integrates the gem5 and gpgpu-sim together. Since the memory controllers are shared among all cores, we observe severe memory contention between them. The CPU applications suffer a 1.26x slowdown and 64.79% blocked time in main memory when they run parallels with GPGPU applications. To alleviate the contention and provide more memory band-width, shared last level caches (LLCs) are commonly employed in such systems. We test a banked shared LLC structure that implanted into the co-simulator. We show that a simple shared LLC contributes mostly to the GPGPU (2.13x to running alone and 1.7x to running in parallel), rather than CPU. With the help of LLC, the memory requests issued to main memory is reduced to 30.74%, the blocked time is reduced to 49.64%, which provides more memory bandwidth. The latency-sensitive CPU applications are suffered as the LLC buffer occupation is very high when they run with GPGPU in parallel. Besides, as the number of LLC cache bank grows, we reveal that CPU achieves higher speedup than GPGPUs by increasing LLC parallelism. Finally, we also discuss the impact of GPGPU L2 cache. And we find that fewer GPGPU L2 cache banks will lower the performance as they limits the parallelism of GPGPU. The observations and inferences in this paper may serve as a reference guide to future CPU-GPGPU shared LLC design.

The trend of increasing on-chip core counts and integrating memory controllers (MCs) makes core-to-memory communication a major obstacle in scaling memory access performance for many-core CMPs. Unmanaged on-chip traffic for long-distance memory accesses, combined with information asymmetry between cores and remote MCs may lead to serious inefficiency in processing massive parallel memory accesses. In this paper we propose a novel agent-based memory access model for CMPs. We employ multiple agents inside the network to assist memory accesses to remote MCs, whose role lies in conducting memory requests from nearby cores, merging some repetitive memory requests and optimizing the scheduling under the backpressure of target MCs. We further describe a simple but effective case for agent-based memory access called Quad Agent, which deploys static agent modules in each quadrant of the network to serve requests towards MCs in other quadrants. The details of memory access merging, scheduling schemes and the architectural supports are discussed. Simulation results show that Quad Agent can reduce memory access latency by 13.3% on average and achieve 20.5% IPC speedup compared with the baseline. The performance promotion is due to increased memory access merge rate, row buffer hit rate and also prevention of traffic congestion and bank starvation.

The shared last-level cache (SLLC) in heterogeneous multicore system is an important memory component that shared and competitive between multiple cores, so how to improve the SLLC performance has become an important research area. Last-level cache (LLC) bypassing technique that bypasses the LLC a part of memory requests is one of the most effective methods. The bypassed requests are sent directly to off-chip main memory (DRAM) rather than eliminated. We find that the bypassed requests influence the original scheduling sequence in Memory Controller (MC) severely. Besides, immoderate bypassing will disturb the MC load balance. We propose a 3-step method memory that adjusts memory scheduling algorithm to optimize LLC bypassing performance. The first step is adding an independent bypass stream for bypassed requests. The second step is scheduling the bypass stream with a smaller probability than that of normal GPU stream. The third step is adding a guard mechanism for MC. By dynamically set and revoke the guard, we can avoid unbalanced bypassing. For case study, we applied the 3-step method on two modern memory schedulers. The experimental results show that after applied the 3-step method, the schedulers improve the system performance obviously.

Speculative Multi-Threading (SpMT) is a promising technology to harness the growing number of cores in modern CPUs by exploiting the available parallelism out of sequential threads. And with SpMT, the inter-dependent fine-grain threads on different cores need to sync their input and output registers. Inter-core register sync is quite expensive, and heavily impacts the overall performance. We propose a conflict-free scheduling to avoid register read/write conflicts among concurrently executing code blocks. Therefore, while executing, the fine-grain threads do not need to sync the input or output registers with each other. Their output registers are still synced across the cores, but only consumed later. Consequently, the register sync and the execution are decoupled, and the inter-core waiting are eliminated or hidden. However, sometimes the conflict-free scheduling does not perform well when there are insufficient conflict-free code blocks to feed all the available cores. We found that, this problem with conflict-free scheduling could be partially fixed by complementing it with the naive scheduling. Experiments with SPEC2006 showed that in most cases (24 out of 29) the improved scheduling (Hybrid scheduling), i.e. The combination of the conflict-free scheduling and the naive scheduling, significantly out performed the naive scheduling.

By exploiting deeply the memory-level and communication-level parallelisms provided by multiple memory controllers (MCs) and interconnect components, NoC-based on-chip distributed memory systems (DMSs) have received great attention to hit the great 'memory wall'. System scaling makes memory access distance and massive contention found in MCs and interconnects critical to system performance. Data replication is a popular optimization method which has been widely employed in multi-socket NUMA systems, last level NUCA caches and cloud systems. In this paper, we explore page repli-cation schemes for NoC-based on-chip DMSs at architectural level. We discuss the external force, internal force and feasibil-ity of establishing page replicas. External force comes from long memory access radius for shared data, which introduces massive memory access traffic. Internal force is derived from overlaps of traffic hotspots and page access centers for globally shared data. High read-write ratios for most significantly ac-cesses pages illustrate the feasibility of replication. According to these observations, we propose models and algorithms to decide the trigger and actual position for establishing replicas and estimate the benefits and overheads. Besides, we discuss some details of content synchronization, replica cancellation schemes. Simulation results show the effectiveness of the sug-gested mechanisms in various scenarios.

With the continuous development of GPUs, modern general-purpose computation on GPUs (GPGPUs) is providing growing parallelism to general programs besides graphics applications. However, for those programs that involve both CPU and GPU, the data transmission bandwidth between them may become bottleneck that prevents GPU from fully exploiting its parallel computing capacity. As to avoid the defect, we try to reduce the data transmission by keeping part of the computation tasks on the CPU side other than sending all the data over to the GPU and process there. In this way the computation is done on CPU and GPU in parallel, and therefore also reduces overall process time. In order to split the computation workload in a systematic approach, we try to divide the corresponding data into chunks of proper size. We experimented our data dividing and heterogeneous memory scheduling with 2 benchmarks. The matrix multiplication is more than 30% faster, and the k means2D is nearly 10% faster, than running solely in GPU.

Developing IC technology makes Network-on-Chip (NoC) an attractive architecture for future systems. Task migration is important for the overall performance of NoCs since the changing system state makes static task mapping improper for NoCs. The predictability of behaviors of applications makes it possible to use prediction to guide task migration. The trigger to initiate task migration is also an important parameter. In this paper, we first defined and analyzed predictabilities of applications using experimental results. We also compared different triggers for migration and concluded that trigger based on packets sent by single node is the best choice. We modified Genetic Algorithm (GA) mapping for migration and proposed 2 algorithms Simple Exchange (SE) and Benefit Assess (BA). A Node Lock mechanism is also used to reduce the number of migrations. These algorithms and node lock are evaluated using real applications. According to the experimental results, SE reduced 78.7% of migrations with 9% less reduction of latency compared to GA; BA reduced 27.2% of latency, It reduced 72.0% of migrations with almost the same performance compared to GA. The node lock mechanism removed 37.3% and 46.0% of migrations in SE and BA with almost the same performance.

WSN is a distributed network exposed to an open environment, which is vulnerable to malicious nodes. To find out malicious nodes among a WSN with mass sensor nodes, this paper presents a malicious detection method based on multi-variate classification. Given the types of a few sensor nodes, it extracts sensor nodes' preferences related with the known types of malicious node, establishes the sample space of all sensor nodes that participate in network activities. Then, according to the study on the type-known sensor nodes' samples based on the multivariate classification algorithm, a classifier is generated, and all of the unknown-type sensor nodes are classified. The experiment results show that as long as the value of sensor nodes preferences and the number of active sensor nodes is stable, the false detection rate is stabilized under 0.5%.

A distributed mobile system consists of a group of heterogeneous mobile devices connected by wireless network. Due to the fact that most of the mobile devices are battery based, the lifetime of a mobile system depends on both the battery behavior and the energy consumption characteristics of tasks. In this paper, we present a set of models for task scheduling in mobile systems equipped with Dynamic Voltage Scaling (DVS) processors. We propose battery-aware algorithms to obtain task schedules satisfying the battery lifetime constraints. The simulations with randomly generated Directed Acyclic Graphs (DAG) show that our proposed algorithms generate better schedules that can satisfy the battery lifetime constraints.

With the growing popularity of 3G-powered devices and their serious energy consumption problem, there are growing demands on energy-efficient data transmission strategies for various embedded systems. Different from the past work in energy-efficient real-time task scheduling, we explore strategies to maximize the amount of data transmitted by a 3G module under a given battery capacity. In particular, we present algorithms under different workload configurations with and without timing constraint considerations. Experiments were then conducted to verify the validity of the strategies and develop insights in energy-efficient data transmission.

Last-level caches (LLC) grow large with significant power consumption. As LLC's capacity increases, it becomes quite inefficient. As recent studies show, a large percent of cache blocks are dead during the cache time. There is a growing need for LLC management to reduce the number of dead block in the LLC. However, there is a significant power requirement for the dead block's in-placement and replacement operations. In this paper, we introduce a global priority table predictor, a technique which is used for determining a cache block's priority when it attempts to insert into the LLC. It is similar to previous predictors, such as reuse distance and dead block predictor. The global priority table is indexed by the hash value of the block address and stores the priority value of the associate cache block. The priority value can be used to drive a dead block replacement and bypass optimization. Through the priority table, a large number of dead blocks could be bypassed. It achieves an average reduction of 13.2% in the number of LLC miss for twenty single-thread workloads from the SPEC2006 suite and 29.9% for ten multi-programmed workloads. It also yields a geometric mean speedup of 8.6% for single-thread workloads and a geometric mean normalized weighted speedup of 39.1% for multi-programmed workloads.

FPGA dynamic partial reconfiguration (DPR) tend to be adopted for its flexibility and fewer resource consumption increasingly in hardware implementation, especially in communication devices. A crossbar scheduling algorithm is used to schedule the crossbar, or decide the order in which cells will be served. The is lip and FIRM are two classic crossbar scheduling algorithms, but they do not support DPR. Performance of these two algorithms differs under varying workloads (load: cells' arrival speed). With the development of DPR, implementations of these algorithms will have improvement both in performance and resource usage. DPR reduces 7.249% average delay than iSlip does and 0.013% average delay than FIRM does in 4×4 crossbar. It reduces 17.9% average delay than iSlip does and 0.039% average delay than FIRM does in 8×8 crossbar. In this paper, we compared the DPR implementation and non-DPR implementations (iSlip and FIRM) and found that the former reduces 37.744% LUTs and 47.874% FFs in 4×4 crossbar, and 47.325% LUTs and 49.907% FFs in 8×8 crossbar.

The memory access stream to the last level cache (LLC) is a filtered version from the upper level caches. There are a large number of cache blocks with long re-reference interval in the LLC. What's worse, zero reuse blocks are in abundance in the LLC and pollute the LLC for a long time. Access pattern based re-reference interval table (RRIT), here we propose, is an efficient management technology for the LLC. RRIT introduces a table to track consecutive blocks' re-reference interval. And then predicts the re-reference interval for a new incoming block. RRIT always selects the block with the max re-reference interval as the victim block when a cache replacement issue occurs. Furthermore, we propose a dead block filtering (RRIT-Filter) mechanism based on RRIT. RRIT-Filter bypasses the predicted dead block and improves LLC efficiency. Our evaluations using the SPEC2006 workloads on a single-core with a 2MB LLC show that RRIT and RRIT-Filter outperform LRU replacement on the throughput metric by an average of 6.6% and 8.6% respectively. Our evaluations with 10 multi-programmed workloads on a 4-core CMP with an 8MB shared LLC show that our strategy outperforms LRU replacement on the throughput metric by an average of 23% and 39% respectively.

As power consumption continues to increase dramatically in real-time systems, the thermal management has become a prominent issue. Taking leakage current into account, this paper focuses on the maximum temperature minimization for the processor executing a set of real-time tasks with a common deadline. We prove that, for a specific interval, constant-speed schedule applying the lowest constant speed will be superior to any other schedule using higher constant speed in maximum temperature minimization. By dividing the interval into two subintervals, we develop a step-down scheduling algorithm, providing each subinterval a unique processor speed to further reduce the maximum temperature. Compared with the optimal constant-speed schedule, the proposed algorithm significantly reduces the maximum temperature by up to 12%.

Chip multiprocessor technique has been implemented in embedded systems due to the tremendous computation requirements. Three dimension chip multiprocessor architecture has been studied recently for integrating more functionalities and providing higher performance. The high temperature on chip is a critical issue for the 3D architecture. In this paper, we propose an online thermal prediction model for 3D chip. Using this model, we present a task scheduling algorithm based on rotation scheduling to reduce the peak temperature on chip. We consider the data dependencies, especially the inter-iteration dependencies which are not well considered in most of the current thermal-aware task scheduling algorithms. Our simulation result shows that our algorithm can efficiently reduce the peak temperature up to 10°C.

Soft error has become an increasingly significant problem in modern computing systems. To overcome soft errors, it has reported that the instruction-level temporal redundancy in out-of-order cores suffers a performance penalty up to 45%. In this work, we propose the fault-tolerant double execution architecture with the fast error correcting code (such as two-dimensional error code) in the instruction reuse buffer. Experimental results show that it gains back IPC loss between 9.14% and 10.15%, with an average around 9.22% compared with the conventional double execution approach.

Attaching reconfigurable loop accelerator to a processor is a promising way to improve the performance and efficiency of the system. It's usually to unroll a loop to increase the parallelism of a loop accelerator. While the higher degree a loop is unrolled, the more reconfigurable area is needed. However, an observation is that the utilization of the loop accelerator is relative to the input. Focusing on the area and performance balance, a dynamically adaptive reconfigurable accelerator framework is proposed on CPU/RA architecture in the paper. Firstly, the inputs are classified into certain predefined types. At run-time the input of the application will be monitored and then the accelerator will be reconfigured to accomplish the area-performance dynamic adaption. An accelerator selection model is also presented to choose an accelerator at run-time according to the predefined input types. And a bzip2 case study is presented, the experimental results demonstrated the feasibility of the approach, and shown that up to 93.6% reconfigurable area is saved at a cost of 1.6% performance lost in a best case.

Network on Chip (NoC) has been proposed as a new paradigm for designing System on Chip which supports high degree of scalability and reusability. Mapping an application, which is described by a parameterized task graph, onto NoC is a key research problem in NoC design. In this paper, we first propose an energy-aware cores mapping approach on WK-recursive NoC, and then present a fast clustering-based scheduling algorithm that maps the cores onto WK-recursive NoC architecture under bandwidth constraints to minimize the total communication energy. Experimental results show that the proposed algorithm is able to handle large task graphs and provide near optimal cores mapping in a few seconds on a PC platform.

The developing semiconductor technology enables the reconfigurable hardware such as FPGA. Distributed reconfigurable system is a FPGA-based hardware accelerated system with network. Applications can be accelerated as hardware module by FPGA in a distributed system. There are few works about application mapping on distributed reconfigurable system. In this paper an application mapping scheme for reconfigurable hardware accelerated distributed system is introduced. By extending the link state routing algorithm, this scheme can maintain the network map with low overhead to ensure the flexibility of the algorithm. The LEFM-NH algorithm proposed in this paper analyzes the current network status and the current application task graphs, and then finds appropriate hosts to map tasks to reduce the average network latency. This paper uses NetFPGA as the reference platform. The LEFM-NH algorithm can reduce the average network latency by 64% compared with simple random mapping algorithm. Experimental results show that the LEFM-NH algorithm of our scheme has good scalability and its execution time has a linear growth with task number.

The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of less reused lines that are never reused or reused for few times. In this case, the cache performance can be improved through retaining a portion of working set in cache for a period long enough. Previous schemes approach this by bypassing never reused lines. Nevertheless, severely constrained by the number of never reused lines, sometimes they deliver no benefit due to the lack of never reused lines.

In camera sensor network research, physical camera sensor network platforms with low power and low cost are needed for testing and validating algorithms. It is also necessary that the camera nodes be calibrated precisely. In this work, we first develop and evaluate a low power and low cost wireless camera sensor network platform. The camera sensor nodes in this platform transmit a grayscale image over a wireless channel to a master control station. Then we propose a simple, light-weight algorithm to perform distributed calibration of the camera sensor nodes. The camera sensor nodes use their imaging abilities in collaboration with a cooperative moving target to determine their own positions and orientations. The proposed algorithm requires simple arithmetic calculations and hence it can be realized on low power processors. This calibration algorithm has been implemented and evaluated on the developed physical camera sensor network platform.

The Intel Cup Undergraduate Embedded System Electronic Design Contest is an embedded system design invitational contest in China. This contest is held every two years since 2002. The contest focuses on the embedded system design and implementation. And it gives undergraduates a chance to show their creativity and learn teamwork. The influence of the contest is keeping increasing. Now it is an international invitational contest. And some universities from the countries which are advanced in computing begin to take part in the contest. In this paper we describe the experiences in such a contest for embedded system.

As the rapidly development of embedded systems, it is a challenge for universities to fill the gap between education and industry. In this paper, we introduce the experiment designed for embedded system curriculum based on embedded IA first, and then adapt the design to the new promising processor-Atom¿ - developed by Intel. At last, we will share our experiences in the experiment teaching of embedded system.

MEMS-based storage device is a new candidate of storage device for pervasive applications which requires large volume of storage. Because of its attractive features such as high-bandwidth, low-power consumption, and low cost compared with hard disk, the storage performance could be significantly improved by adopting MEMS-based storage devices, especially when employing new request scheduling algorithm and data placement A new request scheduling algorithm is explored for MEMS-based storage devices in this paper, which is named parallelism-aware and zone-based shortest positioning time first (PZSPTF). And a new data placement scheme is also introduced, with which the storage area is divided into 2 parts according to 2 file classes, and the files of same class will be stored in the same part. Experiments show that the new PZSPTF algorithm improves the performance of MEMS storage by 7.83% to 18.51% compared with the widely acknowledged request scheduling algorithm FCFS (first-come, first-served).

In order to cope with the energy challenge emerging with the process of parallelism in embedded storing device, this paper focuses on the static code restructuring of nested loop array accessing related to storing device. Departing the running time of different devices can extend the duration time when it is in low- power state. Experiment shows that power-aware code restructuring can effectively reduce state switching times and extra power wasted. Static method described in this paper can achieve up to 12% power reduction if it cooperates with proper dynamic method.

Embedded system has become one of the most important directions in computer education. Embedded system is at the intersection of control system, command and control, wireless data systems, real-time system and so on. The Computer Rank Examination (CRE) is designed to promote the certification for computer application. In this paper, we describe the efforts on embedded education for CRE including the curriculum design and practice.

Nowadays, large storage is becoming an important feature of mobile embedded systems as their media functions are getting increasingly powerful and popular. However, no low power cost memory can provide sufficient capacity at low cost. And much higher power consumption of large capacity storage devices such as Microdrive is hard to be accepted. In this paper, we propose a logical storage layer over hybrid storage device composed of flash memory and Microdrive to provide file systems to embedded systems with minimal impact on battery runtime and power consumption. The result shows that the architecture can provide 32 times as much capacity with 10-15% battery runtime impact.

Abstract: Aiming at the detail rendering in volume data, a new volume illumination model, called Composed Scattering Model (CSM), is presented. In order to enhance different details in volume data, scattering intensity is decomposed into volume scattering intensity and surface scattering intensity with different weight functions. According to the Gauss probability distribution of gray and gradient of data, we propose an accurate method to detect the materials in a voxel, called composed segmentation. In addition, we discuss the principle of constructing these weight functions based on the operators defined in composed segmentation. CSM can generate images containing more details than most popular volume rendering models. This model has been applied to the direct volume rendering of 3D data sets obtained by CT and MRI. The resultant images show not only rich details but also clear boundary surfaces. CSM is demonstrated as an accurate volume rendering model suited for detail enhancement in volume data sets.