A digital camera sensor will incur pixel defects both in fabrication and during its lifetime. While manufacturing defects are corrected in the factory, in-field defects are prohibitively expensive to fix, and can eventually affect the picture quality. During the last 10 years, we have conducted a study of defect development in digital imagers, in which we had access to about 40 cameras and a database of past photos taken by them. The data we collected allows us to quantify characteristics of defect growth. Our investigations have shown that pixel defects are permanent, and their number grows with time. We found that the main type of defect is hot pixels, which are pixels that appear as a bright spot in the image even without any illumination. We also observed that the defects are distributed randomly over the sensor area and are not clustered. By studying past pictures of each given camera we found that the defect growth rate is constant over time. These spatial and temporal characteristics led us to the conclusion that defects are not likely related to material degradation or imperfect fabrication, but are caused by environmental stress such as cosmic rays radiation. Measuring the effect on the defect rate of sensor parameters such as sensor area, number of pixels, pixel size, and sensor technology (CCD - Charge Coupled Device vs. APS - Active Pixel Sensor) yielded a power law, implying that increasing the number of pixels by shrinking the pixel size will result in a higher defect rate and is, therefore, not recommended.

Systems that operate in extremely volatile environments, such as orbiting satellites, must be designed with a strong emphasis on fault tolerance. Rather than rely solely on the system hardware, it may be beneficial to entrust some of the fault handling to software at the application level, which can utilize semantic information and software communication channels to achieve fault tolerance with considerably less power and performance overhead. We show the implementation and evaluation of such a software-level approach, application-level fault tolerance and detection (ALFTD) into the orbital thermal imaging spectrometer (OTIS).

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The interconnection network is a crucial element in parallel and distributed systems. Synthesizing networks that satisfy a set of desired properties, such as high reliability, low diameter and good scalability is a difficult problem to which there has been no completely satisfactory solution. In this paper, we present a new approach to network synthesis. We start by generating a large number of random regular networks. These networks are then passed through filters, which filter out networks that do not satisfy specified network design requirements. By applying multiple filters in tandem, it is possible to synthesize networks which satisfy a multitude of properties. The filtered output thus constitutes a short-list of "good" networks that the designer can choose from. The use of random regular networks was motivated by their surprisingly good performance with regard to almost all properties that characterize a good interconnection network. Experimental results have shown that this approach is practical and powerful. In this paper we focus on the generation of networks which have low diameter, good scalability and high fault tolerance. These generated networks are shown to compare favorably with several well-known networks.

The traditional goals of the floorplanning process for a new integrated circuit have been minimizing the total chip area and reducing the routing cost, i.e., the total length of the interconnecting wires. Recently, it has been shown that, for certain types of chips, the floorplan can affect the yield of the chip as well. Consequently, it becomes desirable to consider the expected yield, in addition to the cost of routing, when selecting a floorplan. The goal of this paper is to investigate the two seemingly unrelated, and often conflicting, objectives of yield enhancement and routing complexity minimization. We analyze the possible trade-offs between the two and then present a constructive algorithm for incorporating yield enhancement as a secondary objective into the floorplanning process, with the main objective still being the minimization of the overall routing costs.

Current very-large-scale-integration (VLSI) technology allows the manufacture of large-area integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in yield-reducing manufacturing defects, whose severity grows proportionally with the size and density of the chip. Consequently, the development and use of yield-enhancement techniques at the design stage, to complement existing efforts at the manufacturing stage, is economically justifiable. Design-stage yield-enhancement techniques are aimed at making the integrated circuit "defect tolerant", i.e., less sensitive to manufacturing defects. They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of defect-tolerant chips must rely on accurate yield projections. This paper reviews the currently used statistical yield-prediction models and their application to defect-tolerant designs. We then provide a detailed survey of various yield-enhancement techniques and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits.

Until recently, VLSI designers rarely considered yield issues when selecting a floorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the floorplan can affect the projected yield. We study several general floorplan structures, make some specific recommendations, and apply them to actual VLSI chips. We conclude that the floorplan of a chip can affect its projected yield in a nonnegligible way, for chips with or without fault-tolerance.

This paper summarizes a practical experiment in designing a defect tolerant microprocessor and presents the underlying principles. Unlike memory integrated circuits, microprocessors have an irregular structure which complicates both the task of incorporating redundancy for defect tolerance in the design and the task of analyzing the resulting yield increase. The main goal of this paper is to present the detailed yield analysis of a defect tolerant microprocessor with an irregular structure which has been successfully fabricated. The approaches employed for achieving the goal of yield enhancement in the data path and the control part of the microprocessor are described first. Then, the yield enhancement due to the incorporated redundancy is analyzed. Finally, some practical and theoretical conclusions are drawn.>

Defect maps of 57 wafers containing large area VLSI IC's were analyzed in order to find a good match between the empirical distribution of defects and a theoretical model. Our main result is that the commonly employed models, most notably, the large area clustering negative binomial distribution, do not provide a sufficiently good match for these large area IC's. Only the recently proposed medium size clustering model is close enough to the empirical distribution. An even better match can be obtained either by combining two theoretical distributions or by a "censoring" procedure in which the worst chips are ignored. Another goal of the study was to find out whether certain portions of either the chip or the wafer had more defects than the others.>

It has been recognized that the yield of fault-tolerant VLSI circuits depends on the size of the fault clusters. Consequently, models for yield analysis have been proposed for large-area clustering and small-area clustering, based on the two-parameter negative-binomial distribution. The addition of a new parameter, the block size, to the two existing parameters of the fault distribution is proposed. This parameter allows the unification of the existing models and, at the same time, adds a whole range of medium-size clustering models. Thus, the flexibility in choosing the appropriate yield model is increased. Methods for estimating the newly defined block size are presented and the approach is validated through simulation and empirical data.>

A wavelength division multiplexing (WDM) transmissive star network is investigated, in which each node has one tunable transmitter with limited tuning capability and multiple fixed receivers. Two synchronous channel access protocols requiring no pretransmission penalty are considered: random access and fixed transmission scheduling. An efficient approximate analysis with drastically reduced computational complexity is presented. In spite of the reduced complexity, the presented approach produces very accurate results and can serve in producing the most cost-effective system design for given performance requirements.>

The authors analyze the performance of multiprocessor systems with a multistage interconnection network in the presence of faulty components. Models for estimating the system performance, as measured by its bandwidth and processing power, are developed for two different modes of operation. In the first mode, the operation of the system is fully synchronized and all processors which require memory access issue their requests simultaneously. In the second, each processor is allowed to issue its request at any time instant. For each of the two modes of operation, two models are presented providing lower and upper estimates for the bandwidth of multistage systems and an upper estimate for their processing power. The operation of 16*16 synchronous and asynchronous reconfigurable systems has been simulated and the bandwidth and processing power have been calculated.>

The authors analyze the performance (over time) of multistage multiprocessors in the presence of faults. A commonly used measure for the performance of an interconnection network is the bandwidth, BW(t), defined as the expected number, at time, t, of requests for the shared memory which are accepted per cycle. They present two models for calculating the bandwidth of the multistage network. These models generalize previously suggested models to allow the presence of faulty links, faulty processors, and faulty memories. The first model is computationally simple but too pessimistic, since it assumes that a memory request blocked by the network is lost. The second model assumes that when a processor's memory request is blocked, it reissues its request in the consecutive network cycle. This model which is computationally more complex, provides an upper estimate for the network bandwidth. The second model allows the calculation of other measures for the system's performance.>

A class of message-based or station-based priority protocols for demand-assignment-based local area networks (LANs), such as Token Bus, HYPERbus, LCN, etc., is defined. It is shown how existing priority protocols can be represented within this class and how they can be extended for a more efficient realization with regard to both delay and capacity of prioritized channel access in LANs. An analytic approach for analyzing multiple-access systems operating under prioritized demand assignment protocols is introduced. The approach permits the modeling of station-dependent and priority-dependent arrival rates and generally distributed transmission times. The introduced finite-population model is especially appropriate for prioritized systems where the number of users per priority class is typically small and users place different service demands on the system. For modeling systems with large populations of users, an approximate model, which is shown to be significantly more computationally efficient than the exact model without imposing additional modeling restrictions, is introduced.>

Demand assignment protocols have been implemented in a large number of operational LANs. However, the analytic models for protocol evaluation currently capture only a limited range of LAN operational circumstances. In this paper we present an analytic tool for evaluating fair and prioritized demand assignment protocols with a relatively general workload model. We consider arbitrary and station dependent message size distributions and arrival rates. This allows the modeling of LANs with heterogeneous workloads, thus permitting a larger correspondence between the modeled system and the real life network.

Recovery procedures involving time redundancy in the form of instruction retries and program rollbacks have proved to be very effective against transient failures in computer systems. A class of such recovery procedures is presented and analyzed here, and the parameters of each procedure are determined so that the system's operation is optimized. These procedures are then compared in order to select the most appropriate one for given system parameters.