This paper describes elements necessary for a general-purpose low-cost very large scale integration (VLSI) neural network. By choosing a learning algorithm that is tolerant of analog nonidealities, the promise of high-density analog VLSI is realized. A 64-synapse, 8-neuron proof-of-concept chip is described. The synapse, which occupies only 4900 mum(2) in a 2-mum technology, includes a hybrid of nonvolatile and dynamic weight storage that provides fast and accurate learning as well as reliable long-term storage with no refreshing. The architecture is user-configurable in any one-hidden-layer topology. The user-interface is fully microprocessor compatible. Learning is accomplished with minimal external support; the user need only present inputs, targets, and a clock. Learning is fast and reliable. The chip solves four-bit parity in an average of 680 ms and is successful in about 96% of the trials.

This paper describes a novel method of representing the three-dimensional MOSFET current table. The method utilizes a template constructed from a drain sweep curve. This template is compressed/expanded and scaled to match all other possible drain sweep curves. This modeling technique provides more than a 10x reduction in storage space requirements, relative to a true three-dimensional table, with little loss in accuracy. It will also be shown that the method can be extended to model the intrinsic charge surfaces.>

Synapse, neuron, and weight increment circuits for a high density, temperature-compensated analog VLSI neural network are introduced. The synapse circuit, which consumes 4500 /spl mu/m/sup 2/ in a 2-/spl mu/m technology, uses hybrid dynamic and non-volatile weight storage. Dynamic memory allows fast learning while non-volatile memory allows reliable long-term storage and low power dissipation. Measured test results for the synapse are presented. The synapse includes a weight increment circuit that adds offset of only 1 part in 16 bits, thus allowing analog-domain on-chip learning using a weight perturbation algorithm. Simple bias circuits cancel temperature dependent parameters in the synapse-neuron transfer function, allowing reliable operation in the temperature range -55 C to 125 C.>

This paper describes concepts that optimize an on-chip learning algorithm for implementation of VLSI neural networks with conventional technologies. The network considered comprises an analog feedforward network with digital weights and update circuitry, although many of the concepts are also valid for analog weights. A general, semi-parallel form of perturbation learning is used to accelerate hidden-layer update while the infinity-norm error measure greatly simplifies error detection. Dynamic gain adaption, coupled with an annealed learning rate, produces consistent convergence and maximizes the effective resolution of the bounded weights. The use of logarithmic analog-to-digital conversion, during the backpropagation phase, obviates the need for digital multipliers in the update circuitry without compromising learning quality. These concepts have been validated through network simulations of continuous mapping problems.

Table-based transistor modeling techniques require a current table and a charge/capacitance table for each device geometry at each simulation temperature. Simple interpolation methods can be used to construct any current table from a small basis set of tables. A database of 32 current tables (two widths, four lengths, measured at four temperatures) is sufficient to span the space defined by these sample points. The technique provides an accurate rendering of the transistor current above threshold without the need for complex parameter optimization and without the need for an exhaustive database of current tables.>

PERC, a custom microprocessor designed for use with an implantable biotelemetry system, is discussed. The system consists of the processor and a number of peripheral chips (such as A/D converters and a telemetry unit) connected through a serial bus. The system requires flexibility in programming, high reliability, and low power consumption. The microprocessor supports these requirements with the ability to be programmed through the telemetry unit and with on-chip timers, on-chip RAM, and special instructions for processing data samples and controlling the system.>

This paper presents a study of precision constraints imposed by a hybrid chip architecture with analog neurons and digital backpropagation calculations. Conversions between the analog and digital domains and weight storage restrictions impose precision limits on both analog and digital calculations. It is shown through simulations that a learning system of this nature can be implemented in spite of limited resolution in the analog circuits and using fixed point arithmetic to implement the backpropagation algorithm.

ZSIM, a nonlinear Z-domain simulator for sampled-data systems, is presented and verified. ZSIM integrates analytic tools, a difference equation simulator, a table-based nonlinear Z-domain simulator, and digital signal processing into a workstation environment to provide fast and accurate simulation of delta-sigma modulators. The use of table-based simulation allows simulation of circuit nonidealities including clock feedthrough and saturation. Benchmark comparisons of difference equation simulations and table-based simulations are presented for delta-sigma modulators suitable for use in voice-band coders.>

The effects of radiation exposure on the performance of CMOS integrated circuits are difficult to predict and to simulate due to the bias-dependent device parameter shifts. Simulation methodologies for identification of failure mechanisms and performance estimation are developed. These simulation algorithms are implemented in the PARA simulator for switch-level simulation of radiation effects. Simulation results for test circuits are presented that prove that accurate estimations are possible without CPU-intensive simulation programs.>

This paper introduces a new method of analysis for Delta-Sigma Modulators based on modeling the nonlinear quantizer with a linerized gain, obtained by minimizing a mean-square-error criterion[7], followed by an additive noise source representing distortion components. In the paper, input-signal amplitude dependencies of Delta-Sigma Modulator stability and signal to noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order Delta-Sigma Modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomenon are explained by the nonlinear analysis of this paper. The analysis is carried out sinusoidal excitations.