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Philip Kaszerman

dblp:45/3477 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 1965
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Theory of computation · 2 · 2 first-authorSystems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Integrated circuit design · 92% Electronic design automation · 8%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design
threshold logic		 0.021965
A "Region" Concept and Its Application to Threshold Logic · Inf. Control. 1965
A Geometric Test-Synthesis Procedure for a Threshold Device · Inf. Control. 1963
Electronic design automation › hardware verification and test › design for testability
test synthesis		 0.011963
A Geometric Test-Synthesis Procedure for a Threshold Device · Inf. Control. 1963
YearPublicationVenuePosition
1965 A "Region" Concept and Its Application to Threshold Logic
Philip Kaszerman
 Inf. Control.1
1963 A Geometric Test-Synthesis Procedure for a Threshold Device
Philip Kaszerman
 Inf. Control.1
1963 A Nonlinear-Summation Threshold Device
Philip Kaszerman
 IEEE Trans. Electron. Comput.1