In this paper, we propose a layout-driven synthesis approach for field programmable gate arrays (FPGA's). The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA. The alternative wires (in the logic level) that can be routed through less congested areas substitute the unroutable wires without changing the circuit's functionality. Allowing the logic blocks to have alternative functions also increases the chance of successful routing. A redundancy addition and removal technique is used to identify such alternative wires. Experimental results are presented to demonstrate the usefulness of this approach. For a set of randomly selected benchmark circuits, on the average, 30-50% of wires have alternative wires. These results indicate that the routing flexibility can be substantially increased by considering these alternative wires. Our prototype system successfully completed routing for two AT&T designs that cannot be handled by an FPGA router alone. The proposed synthesis technique can also be applied to standard cell and gate array designs to reduce the routing area.

This paper shows that cascade circuits in the logic cells of all current lookup table based FP-GAs support only linear cascading chain and, as a result, contribute to long cascading delay.W e present an enhanced cascade circuit that will reduce cascading delay signi cantly: from linear time to log time in terms of the number of logic cells cascaded.We show that the additional area for the new cascade circuit is very small.We discuss an interaction between architecture design decision and CAD (in particular, placement) for the design of dedicated routing structure for cascade signals between logic cells.We illustrate the advantage of the new cascade circuit with an example of 32-bit equality c hecking circuit.

In this paper, we propose a layout driven synthesis approach for Field Programmable Gate Arrays (FPGAs). The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA. The alternative wires (in the logic level) that can be routed through less congested areas substitute the unroutable wires without changing the circuit's functionality. Allowing the logic blocks to have alternative functions also increases the flexibility of routing. The redundancy addition and removal techniques are used to identify such alternative wires. Experimental results are presented to demonstrate the usefulness of this approach. For a set of randomly selected benchmark circuits, on the average, 30%-50% of wires have alternative wires. These results indicate that the routing flexibility can be substantially increased by considering these alternative wires. Our prototype system successfully completed the routing for two AT&T designs that cannot be handled by an FPGA router alone. The proposed synthesis technique can also be applied to standard cell and gate array designs to reduce the routing area.

We &veloped a new meth~called MP2, for partitioning networks into multiple (> 2) blocks each of which has both size and pin constraints.The MP2 method uses an improvement approach snd tries to minimize the total number of terrnintds of tdl blocks while sstistjing the pin and size constraints of every block It supports multiple classes of cells in input networks and blocks.It makes use of a scalar value of benejlt which captures lookshetd information.It is the tit improvement method tbst considers pin constraints of blocks.It has been applied to partitioning tedtrtology-mspped circuits into multiple FFGA chips.In sddhion to describing the MP2 meth~we will discuss some interesting iindings we gleaned during our experiments.

FPGAs (field programmable gate arrays) need not be limited to a single fixed-size truth table in each block. The authors discuss the utility of allowing each block's single large table (e.g. one 5-input, 32-b table) to be reconfigured into smaller tables (e.g. eight 4-b tables). Results describing the efficiency of packing some standard benchmark circuits into various configurations are presented and the cost/benefits discussed. It is shown that a logic block containing four lookup tables, each of which is 8-b RAM, is the best choice if only the area efficiency is considered. It is also shown that if circuit speed is considered, a logic block containing two lookup tables, each of which contains 16 b of RAM, is the best choice.>

As the scope of application of embedded CPUs changes, the design methodologies used to create embedded systems must keep pace. The authors explore what is understood of embedded system design, what problems need to be solved, and novel technologies that may help solve those problems.>

We present an efficient technology mapping method for lookup table-based FPGA architectures.We first introduce lhc notion of edge visibility.Wc then formulate lhc problem of finding the area-optimal technology mapping as a problem of assigning visibility values to edges of input Boolean network to minimize the number of nodes in the network.We describe an algorithm that assigns visibility valtrcs efficiently.We compare our method to the "xl_cover" algorithm provi(ied by the MIS-pga systcm.I. lntrotfttction

We developed a new algorithm for efficient register allocation and binding used in data path synthesis. Our algorithm determines both the number of registers and the mapping from variables to registers simultaneously during data path allocation so that the cost, i.e., area, of the registers and connections to/from the registers can be minimized. The algorithm selects the “best” register for each input and/or output variable of operations. This register allocation/binding algorithm is used with a data path allocation algorithm that exploits trade-off among all kinds of hardware elements. We present experimental results of our algorithm.

A new algorithm of allocating functional units and connections in the data path synthesis has been developed. The algorithm determines the types and numbers of both functional units and connections simultaneously based on their cost (i.e., area) obtained from the input technology data. The algorithm performs trade-off between the functional units and connections to produce data paths with minimal cost. The algorithm is adaptive to different technologies: if the cost of a functional unit changes or if a new functional unit becomes available, the algorithm produces a new data path optimized in the new environment. The algorithm has O(n3) timing complexity in the worst case, where n is the number of operations in the input problem. Experiments show that costs of data paths constructed by our algorithm are smaller than or as much as those by other published approaches.

A combinatorial optimization technique has been developed and applied to the scheduling problem in data path synthesis. The cost function is minimized using a gradient-like method, and constraints are satisfied by a new technique analogous to the combination of the penalty method and the feasible direction method used for nonlinear optimization. To overcome the drawbacks of assigning operations to control steps one at a time, this technique assigns all the operations to control steps simultaneously. Experimental results show that this method is as good as or better than other published methods.>

The design of a hardware unit that performs unification operation is described and analyzed in this paper.In particular, the hardware unification unit is designed to replace the software "unify" function of an existing (UNSW) Prolog interpreter: at the same time.hardware circuits are used extensively to enhance its performance.Based on the design of the hardware unification unit and the statistics obtained from the software 'unify' function, it is shown that the speed of the hardware unification unit is faster than that of the 'unify" function by an order of magnitude.Because the unification is a fundamental operation of Prolog processing and because the 'unify' function is the most time consuming function during query processing, this hardware unification unit can be used to build high performance Prolog machines.

A variation of the tree structure interconnection network for the message switching multiprocessor system is presented in this correspondence. It mainly consists of four binary tree structures, pairs of which are touched by their leaf nodes; in addition, there are four nodes which interface with external environments. The proposed network is left-right and top-down symmetric and is planar. Every node in the interconnection network has the same number of degree, 3. There are multiple paths between any two nodes in the network. Results of the message traffic analysis of the network are presented.