In this paper, we present a physical retiming algorithm for sequential circuits implemented in field programmable gate arrays (FPGAs). This algorithm can speed up the sequential circuits by reducing delay of all critical paths with negative slacks. By taking advantage of the physical information provided by placed circuits, this algorithm integrates two operations: retiming and register duplication. Retiming moves registers across combinational components. Register duplication moves registers across interconnect. Circuit functionality remains unchanged while performing these operations. A concept of timing budget is proposed to guide register moves. An accurate delay estimator for FPGA designs is developed to make register moves much more acceptable compared to conventional retiming technique. Experiments show that the physical retiming algorithm proposed in this paper can effectively reduce the critical path delays, increasing maximum frequency by 13.54%, on average, and improving by 59.54%, on average, the minimum slack for sequential circuits implemented in FPGAs.

We present an ordered tree (O tree) structure to represent nonslicing floorplans. The O tree uses only n(2+[lg n]) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both x and y directions. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is O(n!2/sup 2n-2//n/sup l.5/). This is very concise compared to a sequence pair representation that has O((n!)/sup 2/) combinations. The approximate ratio of sequence pair and O-tree combinations is O(n/sup 2/(n/4e)/sup n/). The complexity of O tree is even smaller than a binary tree structure for slicing floorplan that has O(n!2/sup 5n-3//n/sup 1.5/) combinations. Given an O tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O tree. Empirical results on MCNC (www.mcnc.org) benchmarks show promising performance with average 16% improvement in wire length and 1% less dead space over previous central processing unit (CPU) intensive cluster refinement method.

We present an ordered tree, O-tree, structure to represent non-slicing floorplans. The O-tree uses only n (2 + ⎡lg n⎤) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both x and y direction. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is O(n! 2 2n- 2 / n 1.5). This is very concise compared to a sequence pair representation which has O((n!) 2) combinations. The approximate ratio of sequence pair and Otree combinations is O(n 2 (n /4e) n). The complexity of O-tree is even smaller than a binary tree structure for slicing floorplan which has O(n! 2 5n-3 /n 1.5) combinations. Given an O-tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O-tree. Empirical results on MCNC benchmarks show promising performance with average 16 % improvement in wire length, and 1 % less in dead space over previous CPU-intensive cluster refinement method. 1.

With the recent advent of deep sub-micron technology and new packaging schemes such as multichip modules, integrated circuit components are often not rectangular. Most existing block placement approaches, however, only deal with rectangular blocks, resulting in inefficient area utilization. New approaches which can handle arbitrarily shaped blocks are essential to achieve high-performance design. In this paper, we extend the sequence-pair approach for rectangular block placement to arbitrarily sized and shaped rectilinear blocks. Experimental results show that our algorithm achieves results with excellent area utilization.

With the recent advent of deep sub-micron technology and new packaging schemes such as Multi-Chip Modules(MCMs), integrated circuit components are often not rectangular. Most existing block placement approaches, however, only deal with rectangular blocks, resulting in inefficient area utilization. New approaches which can handle arbitrarily shaped blocks are essential to achieve high performance design. In this paper, we present an approach extending the sequence-pair approach for rectangular block placement to arbitrarily sized and shaped rectilinear blocks. Experimental results show that our algorithm achieves results with excellent area utilization.

We propose an iterative optimization approach for mixedmacro-cell and standard-cell placement, which minimizes the chipsize and interconnection wire length at the same time. We present abranch-and-bound algorithm which efficiently searches for the optimalsolution by evaluating all of the possible configurations on theselected cluster to minimize the gap distance between the ceilingand the floor. A virtual grid and permutation order are generateddynamically to eliminate redundant branches, which was the causeof much higher complexity in other approaches. Experimentalresults on the MCNC benchmark circuits show that the algorithmachieves very competitive results to manual design.