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Miroslav Lícko

dblp:45/3638 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 67% Integrated circuit design · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › FPGA-based signal processing
adaptive filtering		 0.012003
Lattice adaptive filter implementation for FPGA · FPGA 2003
Reconfigurable computing and FPGAs
FPGA-based signal processing		 0.012003
Lattice adaptive filter implementation for FPGA · FPGA 2003
Integrated circuit design › digital circuit design › arithmetic circuit design
logarithmic number system		 0.012003
Lattice adaptive filter implementation for FPGA · FPGA 2003
YearPublicationVenuePosition
2003 Lattice adaptive filter implementation for FPGA
abstract
Our poster introduces an innovative RLS Lattice filter implementation for FPGAs. The signal processing applications typically require wide numeric range, and that poses a problem when using an FPGA implementation. Our approach is based on arithmetic using logarithmic numeric representation (LNS). The test application - an adaptive noise canceller - has been optimized for the Xilinx Virtex devices. It consumes roughly 70% of all logic resources of the XCV800 device and all block memory cells. The filter orders up to 252 at 7 kHz sampling frequency have been achieved using the 19-bit LNS arithmetic. The maximum performance of the application is about 70 MFLOPs including i/o conversions. It has been shown that the custom filter design can be 10 times faster than commonly used solutions. This work was supported by the Ministry of Education of the Czech Republic under Project No. LN00B06.
Zdenek Pohl, Rudolf Matousek, Jirí Kadlec, Milan Tichý, Miroslav Lícko
 FPGA5
2003 MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping
Miroslav Lícko, Jan Schier, Milan Tichý, Markus Kühl
 FPL1