We present an approach to the schematic design and time-dependent simulation of microfluidic systems that are composed of basic components, such as pumps, channels, mixing junctions, and valves. For the schematic capture and the simulation, the Cadence Virtuoso design framework is employed, with the components modeled by Verilog-AMS. The pressures and flow rates are calculated with the help of the hydraulic analogy between electronics and fluidics. Signal flow quantities are used to express the flow of chemical concentration. Our focus is on systems employing chemofluidic transistors, i.e., hydrogel-based microvalves that facilitate autonomous flow control without the need for an external control unit. Our approach also covers layout editing by the use of programmed cells. The utility of the approach is exemplified by the successful top-down design of a chemofluidic oscillator circuit and by the functionally correct simulation of a chemofluidic SR flip-flop.

This paper presents a heterogeneous database hardware accelerator MPSoC manufactured in 28 nm SLP CMOS. The 18 mm2 chip integrates a runtime task scheduling unit for energy-efficient query processing and hierarchical power management supported by an ultra-fast dynamic voltage and frequency scaling. Four processing elements, connected by a star-mesh network-on-chip, are accelerated by an instruction set extension tailored to fundamental data-intensive applications. We evaluate the MPSoC with typical database benchmarks focusing on scans and bitmap operations. When the processing elements operate on data stored in local memories, the chip consumes 250 mW and shows a 96x energy efficiency improvement compared to state-of-the-art platforms.

A hardware implementation of an ADPLL-based clock generator is presented. The digital controlled oscillator (DCO) used in the ADPLL generates a clock signal with a high frequency resolution and a small jitter. The presented ADPLL has a fast acquisition and a large pull-in range. The whole design including the DCO has been described in synthesizable VHDL. It does not contain library specific cells, and can be synthesized independently of the standard cell library. Thus, it is portable and the time required to fit it for different semiconductor processes is reduced considerably. The design adaptation cost is limited to adjustment of a few constants in the VHDL-code. The presented design has been implemented in a V400BG432 VIRTEX FPGA and it has been synthesized using two different standard cell libraries (CMOS AMS 0.6 /spl mu/m and CMOS AMS 0.35 /spl mu/m). The maximum achievable clock frequency is 40 MHz using the FPGA and 52 MHz using the above mentioned standard cell libraries. The maximal lock-in time of the ADPLL is 30 reference clock cycles.

In this paper we propose an architecture for an image sensor with an embedded low-power analog preprocessing unit dedicated for convolution-type filtering. The convolution of the analog image data with the digital convolution kernel is realized using a sequential bit-wise principle. For the subsequent bit-shifted addition a modified current-mode pipelined A/D converter is suggested.