In a typical RTL to GDSII flow, floorplanning or macro placement is a critical step in achieving decent quality of results (QoR). Moreover, in today’s physical synthesis flows (e.g., Synopsys Fusion Compiler or Cadence Genus iSpatial), a floorplan.def with macro and IO pin placements is typically needed as an input to the front-end physical synthesis. Recently, with the increasing complexity of IP blocks, and in particular with auto-generated RTL for machine learning (ML) accelerators, the number of macros in a single RTL block can easily run into the several hundreds. This makes the task of generating an automatic floorplan (.def) with IO pin and macro placements for front-end physical synthesis even more critical and challenging. The so-called peripheral approach of forcing macros to the periphery of the layout is no longer viable when the ratio of the sum of the macro perimeters to the floorplan perimeter is large, since this increases the required stacking depth of macros. In this article, we develop a novel multilevel physical planning approach that exploits the hierarchy and dataflow inherent in the design RTL, and describe its realization in a new hierarchical macro placer, Hier-RTLMP. Hier-RTLMP borrows from traditional approaches used in manual system-on-chip (SoC) floorplanning to create an automatic macro placement for use with large IP blocks containing very large numbers of macros. Empirical studies demonstrate substantial improvements over the previous RTL-MP macro placement approach (Kahng et al., 2022), and promising post-route improvements relative to a leading commercial place-and-route tool.

This paper describes new elements in the RDF-2022 release of the DATC Robust Design Flow, along with other activities of the IEEE CEDA DATC. The RosettaStone initiated with RDF-2021 has been augmented to include 35 benchmarks and four open-source technologies (ASAP7, NanGate45 and SkyWater130HS/HD), plus timing-sensible versions created using path-cutting. The Hier-RTLMP macro placer is now part of DATC RDF, enabling macro placement for large modern designs with hundreds of macros. To establish a clear baseline for macro placers, new open-source benchmark suites on open PDKs, with corresponding flows for fully reproducible results, are provided. METRICS2.1 infrastructure in OpenROAD and OpenROAD-flow-scripts now uses native JSON metrics reporting, which is more robust and general than the previous Python script-based method. Calibrations on open enablements have also seen notable updates in the RDF. Finally, we also describe an approach to establishing a generic, cloud-native large-scale design of experiments for ML-enabled EDA. Our paper closes with future research directions related to DATC's efforts.

In a typical RTL-­to-­GDSII flow, floorplanning plays an essential role in achieving decent quality of results (QoR). A good floorplan typically requires interaction between the frontend designer, who is responsible for the functionality of the RTL, and the backend physical design engineer. The increasing complexity of macro-­dominated designs (especially machine learning accelerators with autogenerated RTL) has made the floorplanning task even more challenging and time­-consuming. In this paper, we propose RTL-­MP, a novel macro placer which utilizes RTL information and tries to "mimic" the interaction between the frontend RTL designer and the backend physical design engineer to produce human-­quality floorplans. By exploiting the logical hierarchy and processing logical modules based on connection signatures, RTL-­MP can capture the dataflow inherent in the RTL and use the dataflow information to guide macro placement. We also apply autotuning to optimize hyperparameter settings based on input designs. We have built RTL­-MP based on OpenROAD infrastructure and applied RTL-­MP to a set of industrial designs. RTL­-MP outperforms state-­of-­the­-art commercial macro placers and achieves QoR similar to that of handcrafted floorplans.

This paper describes the latest release of the DATC Robust Design Flow (RDF), RDF-2021, which has several key additions to expand its horizons. The Chisel/FIRRTL compiler is now part of DATC RDF, enabling support of recent hardware generator designs written in Chisel. Logic locking through RTL obfuscation, an updated ABC synthesis flow, and DFT support are other notable updates to the RDF. A Bookshelf-LEF/DEF converter powered by OpenDB is also added into DATC RDF's inventory as an enabler of robust benchmark conversion. We also describe efforts toward open metrics standards and datasets for machine learning (ML) applications and smart tuning of the design flow, as well as expansion of public analysis calibration data. Our paper closes with future research directions related to DATC's efforts.

This paper introduces VeriGOOD-ML, an automated methodology for generating Verilog with no human in the loop, starting from a high-level description of a machine learning (ML) algorithm in a standard format such as ONNX. The Verilog RTL is then translated through a back-end design flow to GDSII, driven by a design planning approach that is well tailored to the macro-intensive nature of ML platforms. VeriGOOD-ML uses three approaches to build ML hardware: the TABLA platform uses a dataflow architecture that is well suited to non-DNN ML algorithms; the GeneSys platform, with a systolic array and a SIMD array, is optimized for implementing DNNs; and the Axiline approach synthesizes small ML algorithms by hardcoding the structure of the algorithm into hardware, thus trading off flexibility for performance and power. The overall approach explores the design space of platform configurations and Pareto-optimal-PPA back-end implementations to yield designs that represent different tradeoffs at the algorithmic level between area, power, performance, and execution time. The overall methodology, from architecture to back-end design to hardware implementation, is described in this paper, and the results of VeriGOOD-ML are demonstrated on a set of ML benchmarks.

In today's RTL-to-GDS flow domain, there is a lack of standards for reporting of design and tool metrics. Moreover, each tool or engine has its own set of parameters that can change outcomes and trade off PPA and other metrics. Thus, the study and optimization of impacts of parameter settings across the entire RTL- to-GDS tool chain has been largely ad hoc. In this paper, we first describe METRICS2.1, a proposed standard for RTL-to-GDS design tool and flow metrics. We then describe how data collected using a METRICS2.1 realization can be analyzed to give insight into flow tuning and fields of use for PPA optimization. Last, we discuss hyperparameter autotuning in the RTL-to-GDS flow. We present AutoTuner, which uses derivative-free optimization to handle challenges of non-differentiability and many local minima. An open repository based on METRICS2.1 has been established for sharing of reproducible, standardized metrics data, along with example implemented applications, to support academic and industrial research on machine learning for tool/flow tuning.

In this talk, I will analyze the role of placement technology in Physical synthesis. Placement has long been recognized as an important and critical step in the physical synthesis flow. The Placement problem has been researched for the past thirty years and major advancements have been made on this topic. However, most work has focused on placement technology as a point tool.I would like to start off by motivating the need for convergence of placement techniques in two related aspects of the Physical design flow. First, in the RTL or gate level prototyping/floorplanning stage, there is a need for the unification of macro placement and standard cell placement techniques. This requires a placement engine that can operate on a flexible data model. A data model that can simultaneously represent and manipulate objects such as "hard" or "soft" macros, "flexible" clusters or "blobs" of gates or individual standard cells.Second, in the traditional block implementation or "flat physical synthesis" phase, there is a need for convergence of placement, timing analysis and logic optimization. Legacy physical synthesis flows start with a gate level netlist and perform initial timing driven placement. This is followed by in-place optimization of the design where the placed design is optimized by considering transforms such as buffering and gate sizing. In the proposed flow, placement and logic optimization are truly interleaved, which in almost all cases produces a better timing convergence result than the conventional flow. Moreover, there is a strong relation between the above two scenarios in developing a robust Chip level Physical Synthesis syste.In conclusion, even though there can be further research done on new placement algorithms, it makes more sense on using the existing research and concentrating on producing better and robust physical synthesis flows, flows that can perform both as prototyping/floorplanning environments in the front end and implementation environments in the back end.

Regularity extraction is an important step in the design flow of datapath-dominated circuits. This paper outlines a new method that automatically extracts regular structures from the netlist. The method is general enough to handle two types of designs: designs with structured cluster information for a portion of the datapath components that are identified at the HDL level; and designs with no such structured cluster information. The method analyzes the circuit connectivity and uses signature based approaches to recognize regularity.

Hierarchical compaction requires that a system of linear equations be solved, usually via linear programming (IE) techniques.In the presence of overconstraints, LP techniques provide inadequate information to locate the cause of these overconstraints.A new graph theoretical method capable of identifying overconstraints and providing meaningful feedback to the user is described.The method also considerably reduces the number oj equations to be solved by LPI making %gompaction of very large layouts possible.

A method for efficiently performing hierarchical compaction in the presence of over the cell routing (OTCR) is described. By treating the OTCR objects as part of the cells they overlap, the amount of interaction between cells in the hierarchy is reduced. This method eliminates the need to make all objects within a cell that interact with OTCR into ports. An explosion in the complexity of the problem that needs to be solved via linear programming (LP) is thus avoided. Computation is shifted away from LP and into the graph domain where efficient and accurate solution methods have been demonstrated.>

Abstract We consider the problem of transferring a set of files from their given locations in a fully connected network to their respective target locations in minimum time. We show that this problem is NP‐hard even with the restriction that no file uses more than two edges in its route. We present an efficient algorithm to solve this problem in the case when there is only one source and one or more destinations. For the general case, we propose a two‐phase approach to find two‐edge schedules that are optimal or close‐to‐optimal. In Phase I, two‐edge routes are assigned to files; in Phase II, a schedule is determined for the use of the links in these routes. For Phase I, we present an exact solution that is based on integer programming formulation and also give theoretical bounds for approximate solution. We also propose a route assignment algorithm that attempts to assign routes of minimum congestion. For Phase II, we present an efficient algorithm that constructs a schedule from the solution obtained in the first phase.

In this paper, we bound the complexity of the major algorithms of 1-d compaction in graph solution and module assembly to be Ο(n15logn). An 1-d hierarchical module assembly method is shown to be free from the x-y interlock problem and achieves significant improvement in space and time requirements by exploiting hierarchy.

In a distributed database system there is a need for periodic changes in data distribution due to such factors as changes in query patterns and network topology. A proper redistribution of data is necessary to provide acceptable system performance, as measured by the average execution time of transactions. The problem of properly scheduling data transfers in order to complete this redistribution process in minimum possible time is investigated. This problem takes into account the constraints on communication resources of the system. The complexity of the problem is discussed, and a useful upper bound for optimal solutions is presented. Also given are procedures for finding optimal and approximate solutions to this problem.>