This paper introduces an Artificial Neural Network (ANN) to predict the stability of Delta-Sigma modulators (DSMs) and, furthermore, shows its beneficial employment in a genetic optimization algorithm. Since a DSM is a non-linear system, its stability often can’t be predicted by simple algebra. Therefore, a new approach predicting the stability of DSMs using an ANN is presented in this work. It is shown how the data generation and training of such a network can be done. Furthermore, the derivation of high-level coefficients for DSMs is a tedious task, which is often solved by time consuming simulations. The application of the derived ANN in a genetic algorithm to find these high-level coefficients leads to the significant time savings of close to 50%.

In this paper, the linear-exponential incremental Delta-Sigma (I-DS) ADC is analyzed as a dynamic reconfiguration technique. The influence of the parameters of the exponential phase on the performance of the ADC will be analysed and further investigated under the presence of coefficient mismatch. Furthermore, higher order linear-exponential I-DS ADCs will be introduced and the analysis is extended from first to higher order modulators, giving valuable insights and showing the benefits and drawbacks of higher order linear-exponential I-DS ADCs compared to first order ones. The intention is to give an insight and understanding of the performance improvements, limiting factors and trade-offs achieved by the exponential phase.

In this paper, analysis of linear time-variant systems is applied to incremental Delta-Sigma (I-DS) ADCs with periodic architectural reconfiguration in the frequency domain. The analysis will then be applied to the example of linear-exponential I-DS ADCs as a state-of-the-art dynamic reconfiguration technique. It is shown how a matched reconstruction filter of the reconfigured linear-exponential incremental Delta-Sigma modulator (I-DSM) can be mathematically derived. Using the calculated overall transfer functions of the linear-exponential I-DS ADC, accurate performance predictions can be given. The proposed method allows the accurate prediction of performances and gives insight and understanding of the performance improvements and trade-offs achieved by reconfiguration techniques in I-DS ADCs in general and the exponential phase in particular.

In this paper the heuristic-search based design of Sigma-Delta modulators with FIR feedback is described. Using single-bit quantizers in Sigma-Delta modulators (SDMs) is very common due to their inherent linearity. However, their binary feedback increases the requirements for the integrators and the jitter sensitivity in the loop compared to multi-bit feedback. FIR feedback tries to resolve these problems, however, requires a second compensating FIR filter and an adjusted loopfilter scaling in order to restore the original noise transfer characteristic. This not only makes the design process more challenging but also leads to increased peaking of the STF, undesirable for many applications. Therefore, in this work a heuristic-search based design approach is presented which offloads work from the designer to an automated design environment. It allows to design CT SDMs directly in the CT domain including the compensation of nonidealities and STF engineering in order to counteract the peaking. The theoretical background is described as well as the additions to the underlying design framework. Alongside, design examples are given to illustrate the advantages of this approach.

This paper analyzes the effect of signal transfer function (STF) peaking in continuous-time (CT) Delta-Sigma- Modulators (DSMs) arising from excess loop delay (ELD) and its compensation. Starting from a generic model, the origin of different contributors to STF peaking are revised, namely noise transfer function (NTF) peaking due to aggressive noise shaping, instability from uncompensated delay as well as forward loop filter zeros in cascade-of-integrators with distributed feedforward (CIFF) modulators. The shift of forward loop filter zeros as a result of ELD compensation is shown intuitively for a 3rd order example, while system-level simulations of various 2nd, 3rd and 4th order CT single-loop modulators confirm increased STF peaking in the above stated scenarios.

Incremental Sigma-Delta (ΣΔ) modulators inherit internal oversampling and noise-shaping properties of a conventional ΣΔ modulator. However, by resetting its internal states, as well as the digital reconstruction filter after certain number of clock cycles, a sample-by-sample conversion behavior is obtained and the modulator can be considered as a Nyquist-rate converter. Multibit architectures allow for low oversampling ratios and can be very attractive for high speed applications. Yet, it comes with digital-to-analog converter (DAC) linearity concerns and commonly used linearization techniques such as dynamic element matching are inefficient when acquired in an Incremental ΣΔ modulator, due to the resetting environment and especially for very low OSRs. This paper presents an enhanced incremental sturdy multi-stage noise-shaping ΣΔ modulator structure, which utilizes a variable quantizer bit width in the second stage for linearity improvement. The behavioral simulations of the proposed architecture show its robustness against DAC mismatch, achieving 25 dB improvement in total harmonic distortion in the presence of 0.1% DAC element mismatch with an OSR of 35.

This demo shows the automated high-level design process of continuous-time bandpass ΣΔ modulators with the web-based design tool www.sigma-delta.de. The design methodology presented in this demo is based on a heuristic search which allows to directly account for major non-idealities as excess-loop-delay, finite bandwidth and finite DC gain. In contrast to other state-of-the-art design methodologies, it allows to include specifications for the STF and is not just focused on the optimization of the NTF in order to achieve a high SNR. In this demo the visitors get to know the capabilities of the tool and a general insight is given with the possibility of hands-on experience. The workflow - with a fast response such that the visitors can generate their own modulators in real time - is illustrated with matching examples.

This paper presents a state-of-the-art overview and recent advances on circuit and system level design methods and EDA tools for the automation and optimization of Delta-Sigma (ΔΣ) modulators. Main synthesis strategies and techniques are highlighted, putting emphasis on those aspects, which need to be taken into account in order to maximize the performance of ΔΣconverters, while keeping computational efficiency high. Based on the comparison of the approaches considered in this survey, the authors try to answer, where man or machine can come in1.

Clock jitter sensitivity is a well-known drawback of continuous-time ΣΔ modulators. Although there exist various methods to alleviate the jitter influence, most are only effective in reducing noise incurred by out-of-band quantization noise. However, due to the steadily increasing signal frequency in receiver applications, the dominant jitter influence rather originates from the mixing between the close to in-band interferers and the close-in clock phase noise, either in a mixer or in the DAC of a bandpass ΣΔ modulator. This mixing results in additional in-band noise which cannot be reduced by existing solutions. In this paper, we use a reconfigurable digital filtering method for close to in-band interferer suppression in bandpass ΣΔ modulators, and demonstrate its effectiveness in improving phase noise tolerance through simulation. Additionally, a technique to simplify the implementation of the digital filters is proposed.

In this paper the automated design of continuous-time bandpass ΣΔ modulators with arbitrary signal-transfer-functions is described. State-of-the-art design methodologies rely on multiple transformations to obtain continuous-time bandpass modulators. Moreover, they are mainly focused on the NTF in order to achieve the required SNR. A design approach, which allows to realize a specified signal-transfer function is not known in the state-of-the-art. In contrast to that the web-based design tool www.sigma-delta.de allows STF engineering for bandpass modulators as first of its kind. The STF is optimized with regard to user defined specifications while the signal-to-noise ratio of the modulator is maximized. This work gives a general introduction to the tool and explains the features concerning bandpass modulators in detail together with corresponding examples.

For two decades, Excess-Loop-Delay (ELD) is known to degrade the performance of continuous-time (CT) ΣΔ A/D converters. Many methods have been proposed to compensate for this effect, but for their implementation sophisticated knowledge in loop-filter design is necessary. The web-based design tool for CT ΣΔ modulators www.sigma-delta.de offers a straightforward integration of commonly used ELD compensation techniques in an early stage of the design process without the need of in depth knowledge of ΣΔ loop-filters. As the tool uses a heuristic search, based on a genetic algorithm within a parallel implementation on a GPU, it provides results with a very short response time. This paper presents the compensation techniques which are commonly implemented within the state of the art and shows their automatic application on architectural level by the design tool. Exemplary modulators are created and evaluated in a circuit level simulator. Further, the calculation of device parameters for a circuit-level simulator model, based on the coefficients obtained by the tool, is illustrated. Thereby, the usage of the developed and publicly available design tool for CT ΣΔ modulator is practically shown.