Special-purpose architectures have been proposed to provide high processing rates for signal processing applications. These architectures use highly concurrent structures on VLSI circuits to achieve billions of multiply/add operations per second. Both serial-parallel and fully bit-serial multiplier elements have been proposed for highly concurrent signal processing arrays. Error detection can be accomplished by applying arithmetic codes to the multiplier hardware in different ways. Here, low-cost residue codes are applied to three different error detection architectures for both serial-parallel and fully bit-serial processing elements. The error performance of these different implementations is studied through computer simulation. The cost of using these codes in terms of silicon area and circuit complexity is also investigated.>

A novel methodology for investigating wafer-scale integration (WSI) designs is proposed. This methodology combines the results of work on integrated circuit yield modeling with a study of the effects of system architecture in large-area integrated circuit yield. This work provides a hierarchical framework in which computing structures may be analyzed to determine functionality on a wafer scale and develops methods by which this functionality can be optimized.>

Bit-sequential algorithms for arithmetic processing are good candidates for VLSI signal processing circuits because of their canonical structure and minimal interconnection requirements. Several recent papers have dealt with algorithms that accept unsigned binary inputs, one bit at a time, least significant bit first, and produce an unsigned binary product in a bit-serial fashion.

At the present time substantial software, memory, and CPU cycle penalties are incurred in bridging the semantic gap between high-level language formatted output statements and I/O device capabilities. Because of this gap and in response to the rapidly expanding capability of VLSI microelectronic circuits, a dedicated I/O processor is proposed to off-load the inherent conversion and formatting task from the host computer. The research reported here investigated the feasibility, the architectural requirements, and the implementational considerations of a regular design methodology for a VLSI-based I/O formatter.

Increasing digital signal processing requirements coupled with developing VLSI circuit capabilities suggest that new architectures may be necessary for many signal processing applications. These new architectures must be compatible with the high density and planar layout features of VLSI circuits. Characteristics of parallel and serial multipliers for high-speed digital signal processing are discussed along with their respective implications for VLSI circuit realizations. Advantages of a bit-sequential approach to large-scale digital signal processors are presented, and the characteristics of a single-chip design for an image filter with 16, 12×12-bit multipliers followed by a tree adder structure are summarized.

This correspondence suggests an improved double buffering algorithm for two bubble memory architectures suggested in a recent paper1 by Doty et al. The new method is more general than the original and results in a faster memory scan time.