A methodology to evaluate transient-fault effects on synchronous and asynchronous is presented in this work. It is developed by means of fault-injection simulation campaigns on gate-level circuit implementations. The methodology is able to deal with the particularities of asynchronous circuits. Unlike previous works, it permits to compare the sensitivity of circuits designed by synchronous and asynchronous logics. The resultant metrics allow identifying at high-level abstraction what is the logic that makes the circuit more transient-fault sensitive. As a case study, a crypto-processor in versions synchronous and asynchronous was evaluated.

Asynchronous circuits are often claimed as being an interesting alternative to design robust systems against faults. In this study, a method is proposed to model the behavior of quasi delay insensitive (QDI) asynchronous circuits in the presence of SEUs (memory bit flips). The circuits and the fault injection process are both described using this model. The method, based on symbolic simulation, consists of exploring all the reachable states in the presence of faults in order to draw up an exhaustive list of behaviors. A case study shows that this method enables us to verify some properties on the circuits. SEU resistance can be formally proven using this analysis.

This paper presents practical results on the evaluation of fault countermeasures implemented in an asynchronous DES coprocessor. The theory underlying the countermeasures was previously published in IOLTS 2005. For the first time this work reports a practical evaluation of fault countermeasures applied on asynchronous DES ASICs. Two DES crypto processors were fabricated using the 130 nm STmicroelectronics CMOS process; one as a reference and one hardened using a specific technique. This work enables us to compare the resistance of both circuits against fault injection and to validate the proposed countermeasures. The practical set-up of the fault injection, using a laser, is presented and the test campaign described. The practical results prove the efficiency of the method. The techniques can be applied to protect logic blocks in any applications.

The problem of fault tolerance and fault resistance is becoming more and more important in all application fields. In this context, asynchronous designs provide inherent properties that make them attractive to design robust systems. Moreover, hardening techniques can be applied at the design time to improve their fault resistance with low area, speed and power costs. This work presents the latest characteristics analysis and conclusions on the potential of asynchronous circuits for both security and safety designs. It clearly demonstrates that the asynchronous technology enables the design of efficient fault tolerant/resistant integrated circuits

This paper presents hardening techniques against fault attacks and the practical evaluation of their efficiency. The circuit technology investigated to improve the resistance against fault attacks is asynchronous logic. Specific properties of asynchronous circuits make them inherently resistant against a large class of faults. An analysis of their behavior in the presence of faults shows that they are an interesting alternative to design robust systems. A behavior diagnosis enables us to propose hardening techniques that improve fault tolerance and resistance. They are applied at design time and aim at exploiting quasi-delay insensitive (QDI) circuit properties to significantly harden the architecture with a very low area overhead and a reasonable performance penalty. To validate these techniques, a hardened DES crypto-processor is presented. The countermeasures are evaluated using laser beam fault injection

This paper presents a transient faults sensitivity evaluation for Quasi Delay Insensitive (QDI) asynchronous circuits. Because of their specific architecture, asynchronous circuits have a very different behavior than synchronous circuits in the presence of faults. We address the effects of transient faults in QDI circuits and describe the causes that lead the faults to be memorized into one or more soft errors. Therefore, a refined fault sensitivity criterion is defined for this class of circuits. This methodology enables us to point out the weak parts of a circuit. An analysis tool is implemented to support this evaluation. This tool provides a quantitative study of the fault sensitivity, and enables us to compare the robustness of different architectures of a circuit along the steps of its design flow. The objective of this work is to evaluate the circuits robustness against natural faults (single fault model) and intentional fault injection (multiple faults model).

This paper presents hardening techniques against transient faults for quasi delay insensitive (QDI) circuits. Because of their specific architecture, asynchronous circuits have a very different behavior than synchronous circuits in the presence of faults. We address the effects of transient faults in QDI circuits and describe consequences on the circuit behavior. Three techniques exploiting QDI circuit properties are proposed for hardening. These techniques improve the tolerance to transient faults, and make their detection easier. These techniques are compared in terms of efficiency and cost.