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Hosung Kim

dblp:45/5390 · DBLP profile ↗
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13ranked-venue papers
8as first author
3since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 10 · 7 first-author · 2 since 2021Graphics, computer vision, multimedia, augmented reality and games · 8 · 6 first-author · 1 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › logic synthesis
FPGA synthesis
0.112008
A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation
physical design
0.012008
A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › physical design › placement
post-placement optimization
0.012008
A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008

Methods — techniques the papers use, named apart from their topics

mini-LUT tree mapping · 0.1functional decomposition · 0.1dynamic programming · 0.1
YearPublicationVenuePosition
2026 Task-aware evolution in physics-informed neural networks: Application to Saint-Venant torsion problems
Su Yeong Jo, Jeesuk Shin, Jongcheon Park, Hosung Kim, Seungchan Ko, Sangseung Lee, Joongoo Jeon
Eng. Appl. Artif. Intell.5
2026 SurfGNN: A robust surface-based prediction model with interpretability for coactivation maps of spatial and cortical features
Zhuoshuo Li, Jiong Zhang 0004, Youbing Zeng, Dan Zhang 0026, Jianjia Zhang, Duan Xu, Hosung Kim, Bingguang Liu
Medical Image Anal.8
2021 Style Transfer Using Generative Adversarial Networks for Multi-site MRI Harmonization
Piyush Maiti, Sophia I. Thomopoulos, Alyssa H. Zhu, Yaqiong Chai, Hosung Kim, Neda Jahanshad
MICCAI (3)6
2017 Surface-Wise Texture Patch Analysis of Combined MRI and PET to Detect MRI-Negative Focal Cortical Dysplasia
Hosung Kim, Yee-Leng Tan, A. James Barkovich, Duan Xu, Robert Knowlton
MICCAI (1)1
2016 A Surface Patch-Based Segmentation Method for Hippocampal Subfields
Benoît Caldairou, Boris C. Bernhardt, Jessie Kulaga-Yoskovitz, Hosung Kim, Neda Bernasconi, Andrea Bernasconi
MICCAI (2)4
2015 NEOCIVET: Extraction of Cortical Surface and Analysis of Neonatal Gyrification Using a Modified CIVET Pipeline
Hosung Kim, Claude Lepage, Alan C. Evans, A. James Barkovich, Duan Xu
MICCAI (3)1
2014 Multivariate Hippocampal Subfield Analysis of Local MRI Intensity and Volume: Application to Temporal Lobe Epilepsy
Hosung Kim, Boris C. Bernhardt, Jessie Kulaga-Yoskovitz, Benoît Caldairou, Andrea Bernasconi, Neda Bernasconi
MICCAI (2)1
2012 Surface-based multi-template automated hippocampal segmentation: Application to temporal lobe epilepsy
Hosung Kim, Tommaso Mansi, Neda Bernasconi, Andrea Bernasconi
Medical Image Anal.1
2011 Vertex-Wise Shape Analysis of the Hippocampus: Disentangling Positional Differences from Volume Changes
Hosung Kim, Tommaso Mansi, Andrea Bernasconi, Neda Bernasconi
MICCAI (2)1
2011 Robust Surface-Based Multi-template Automated Algorithm to Segment Healthy and Pathological Hippocampi
Hosung Kim, Tommaso Mansi, Neda Bernasconi, Andrea Bernasconi
MICCAI (3)1
2008 Surface-Based Vector Analysis Using Heat Equation Interpolation: A New Approach to Quantify Local Hippocampal Volume Changes
Hosung Kim, Pierre Besson, Olivier Colliot, Andrea Bernasconi, Neda Bernasconi
MICCAI (1)1
2008 A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs
abstract
It is well known that optimizations made by traditional logic synthesis tools often correlate poorly with post-layout performance; this is largely a result of interconnect effects only being visible after layout. In this paper, acorrectivemethodology is proposed for timing-driven logic restructuring at the placement level. The approach focuses on a lookup table (LUT)-based field programmable gate arrays. The approach is iterative in nature. In each iteration, using current placement information, the method induces a timing-critical fan-in tree via (temporary) replication. Such trees are then reimplemented where the degrees of freedom include functional decomposition of LUTs, ldquomini-LUTrdquo tree mapping, and physical embedding. A dynamic programming algorithm optimizes over all of these freedoms simultaneously.Allsimple disjoint LUT decompositions (i.e., Ashenhurst style) are encoded in a ldquomini-LUTrdquo tree using choice nodes similar to those in the paper by Lehman At the same time, because embedding is done simultaneously, interconnect delay is directly taken into account. Over multiple iterations, the design is progressively improved. The framework has been implemented, and promising experimental results are reported.
Hosung Kim, John Lillis
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2001 Requirements-Based Dynamic Metrics In Object-Oriented Systems
abstract
Because early design decisions can have a major long term impact on the performance of a system, early evaluation of the high-level architecture can be an important risk mitigation technique. This paper proposes a technique for predicting the volume of data that will flow across a network in a distributed system. The prediction is based upon anticipated execution of scenarios and can be applied at an extremely early stage of the design. It is driven by requirements specifications and captures dynamic metrics by defining typical usage patterns in terms of scenarios. Scenarios are then mapped to architectural components, and dataflow across inter-partition links is estimated. The feasibility of the approach is demonstrated through an experiment in which predicted metrics are compared to runtime measurements.
Jane Cleland-Huang, Carl K. Chang, Hosung Kim, Arun Balakrishnan
RE3