In this article, we derive a practical limit on the maximum achievable selectivity of three commonly used Passive Switched-Capacitor (PSC) Infinite-Impulse Response (IIR) low-pass filter (LPF) topologies driven from a resistive source. We show that filter topology selection and component dimensioning aimed to improve the selectivity of these filters will necessarily degrade the Noise Figure (NF), revealing a selectivity versus NF trade-off. We subsequently capture this in selectivity versus NF graphs. These graphs quantify the limitations on achievable selectivity and NF for each topology given the number of filter poles, and graphically provide guidance in navigating the trade-off between them. The three considered topologies mainly differ in how the sampling capacitor resets, inverts, or holds its voltage between clock periods. We capture the handling of the sampling capacitor as a new design parameter. We derive a singular model to encompass the entire design space consisting of the three topologies, filter order (number of history/integration capacitors), clock frequency, and component dimensions. The model comprises an adjoint network with a state-space description and is used to analyze the filter transfer function (to quantify selectivity), input- and output-referred noise, and NF.

This paper describes the design and implementation of a 4 MHz bandwidth$3{^{\text {rd}}}$-order Discrete-Time (DT) Passive Delta-Sigma Modulator (${\mathrm {P\Delta\Sigma M}}$), which avoids the use of supply voltage-sensitive linear amplifiers. The Switched-Capacitor (SC) operation and amplifier-less nature of its loop filter render the proposed modulator highly supply voltage- and clock frequency-flexible. To explain our design choices, we investigate two key design challenges unique to${\mathrm {P\Delta\Sigma M}}$s. Firstly, the noise criticality of the quantizer ADC due to the lack of (voltage) gain in the loop filter preceding it. Secondly, the inaccessibility of the readily synthesizable and highly frequency-selective loop filter frequency responses typically employed in${\mathrm {\Delta\Sigma M}}$s, caused by the absence of linear amplifiers. We show that the noise-power trade-off of the quantizer ADC in 1 bit P$\Delta \Sigma $Ms is the same as that of the first integrator amplifier in Active${\mathrm {\Delta\Sigma M}}$. Next, we cover the suitability of several passive filters for use in${\mathrm {P\Delta\Sigma M}}$loops. This leads to the selection of the voltage-sampled Charge-Rotating IIR (CR-IIR) filter, for which we show${\mathrm {\Delta\Sigma M}}$-oriented design equations, on which we base the design of our$3{^{\text {rd}}}$-order DT${\mathrm {P\Delta\Sigma M}}$. Measurement results on the resulting prototype${\mathrm {P\Delta\Sigma M}}$, implemented in GlobalFoundries 22 nm FD-SOI CMOS, demonstrate that it achieves a 71.9 dB peak SNDR and 4 MHz bandwidth while consuming 4.4 mW from a 0.9 V supply and occupying 0.076 mm$^{\mathrm {\mathbf {2}}}$of silicon area. The prototype${\mathrm {P\Delta\Sigma M}}$continues to operate at a$2.25\times $reduced supply voltage of 0.4 V, albeit at a reduced bandwidth of 156.25 kHz, where it achieves a peak SNDR of 62 dB while consuming 37.8$\mu $W.

In this paper, the CMOS inverter chain buffer is optimized for N-path filter switch drivers in a technology-agnostic way. Figures-of-merit are proposed to minimize jitter for minimal power dissipation with consideration of rise/fall-time. Using these, mathematical models are derived based on a simple circuit model and expressed for optimization as a function of the technology-specific inverter output/input capacitance ratio, the number of inverters, and their taper factors. This enables finding designs with any set of taper factors that have lower jitter than common designs for the same power dissipation by sweeping many designs orders of magnitude faster than using circuit simulations. Additionally, analytical equations are derived to quickly allow a designer to find the optimal number and sizing of inverters for the constant and exponential taper designs, either of which is shown to be near-optimal depending on the set of specifications.

Voice Activity Detection (VAD) is a technique used to identify the presence of human voice in an audio signal. It is implemented as an always-on component in most speech processing applications. As speech is absent most of the time, this component typically dominates the overall average power consumption of the system (excluding microphone). The widespread usage in speech applications and the need for ultra low power VAD have led to a plethora of algorithms and implementations in the hardware domain, necessitating a comprehensive study and analysis to understand (real-time) requirements, different design parameters, testing strategies, but also to identify design trends, challenges and guidelines for future implementations and testing of VAD devices. A scoping review was conducted to identify the articles for hardware implementations of VAD from January 2010 - December 2021, the results of which are presented in this article. The results highlight a big design space being used for VAD along with a lack of standard testing methodology and usage of application-dependent performance metrics. An increased usage of filter-based feature extractors along with neural-network-based classifiers is observed. Due to lack of standardisation, no other trends can be established from the results. A set of rules and guidelines are therefore provided to facilitate the future development and benchmarking of VADs.

A novel algorithm is presented that can resolve frequency ambiguity that arises from sampling a set of signals spanning more than a single Nyquist zone. The method uses two samplers, each sampling the same input signal with different (non-integer multiple) sampling rates. The algorithm is able to resolve frequency ambiguity and reconstruct signals with an orthogonal frequency basis spanning multiple Nyquist zones, provided that the aggregate information-bearing bandwidth of the signals is less than half the cumulative data converter sampling rates. This manuscript describes the theoretical background for the algorithm and validates it through measurements performed on a test-board comprising of two 10 bit analog-to-digital converters clocked at two different (non-integer multiple) sample rates. Measurements show that even in the presence of aliasing, an orthogonal signal spanning multiple Nyquist zones can be fully reconstructed.

Digital Multiple-Input Multiple-Output (MIMO) receivers, exposed to strong co-channel interference, require high dynamic range Analog-to-Digital Converters (ADCs) and a highly linear RF front-end. Hybrid analog-digital beamforming can mitigate this co-channel interference by spatial filtering before the ADC and improve interference robustness. This paper demonstrates and characterizes this mitigation effect in detail utilizing Error Vector Magnitude (EVM) as a criterion. A 4-element 22 nm FD-SOI CMOS prototype MIMO Receiver chip is characterized with a linear 4-element dipole antenna array with half-wavelength spacing in the 2.4 GHz ISM-band. EVM measurements demonstrate the effectiveness of spatial filtering for co-channel interference mitigation and dynamic range extension. The receiver is exposed to interference while using different QAM formats (16-QAM to 256-QAM). It is demonstrated how interference reduces the acceptable-EVM input power range, while hybrid beamforming extends this range. This is done by extensive conductive measurements for reliable results, while also demonstrating an Over-the-Air (OTA) result.

In-band full-duplex sets challenging requirements for wireless communication radios, in particular their capability to prevent receiver sensitivity degradation due to self-interference (transmit signals leaking into its own receiver). Previously published self-interference rejection designs require bulky components and/or antenna structures. This paper addresses this form-factor issue. First, compact radio transceiver feasibility bottlenecks are identified analytically, and tradeoff equations in function of link budget parameters are presented. These derivations indicate that the main bottlenecks can be resolved by increasing the isolation in analog/RF. Therefore, two design ideas are proposed, which provide attractive analog/RF-isolation and allow integration in compact radios. The first design proposal targets compact radio devices, such as small-cell base stations and tablet computers, and combines a dual-port polarized antenna with a self-tunable cancellation circuit. The second design proposal targets even more compact radio devices such as smartphones and sensor network nodes. This design builds on a tunable electrical balance isolator/duplexer in combination with a single-port miniature antenna. The electrical balance circuit can be implemented for scaled CMOS technology, facilitating low cost and dense integration.

Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter and/or phase noise is an important quality criterion for synthesizers. This paper reviews fundamental limitations for jitter in digital frequency architectures, aiming at finding a basis to compare alternative architectures and optimize jitter performance. It motivates why the product of jitter variance and power consumption is a useful figure of merit (FoM) for optimization, based on fundamental physical limitations. Applying this FoM to multi-phase clock generation leads to the conclusion that circuits with low delay are preferred, favoring a shift register architecture ("ring counter") over a Delay Locked Loop. For a PLL a Jitter-Power FoM is also defined and we show that significant improvements have been made during recent years.

This work proposes a direct conversion transmitter architecture intended for cognitive radio applications. The architecture is based on the poly-phase multipath technique, which has been shown to cancel out many of the harmonics, sidebands and nonlinearity contributions of a power up converter using a large number of signal paths. This work proposes a design only using 8 paths which is able to achievethand 9thharmonic. This is done with a combination of duty cycle control of the Local Oscillator (LO) waveform and tunable filtering with only a first order roll-off.

Spectrum sensing is one of the key characteristics of a cognitive radio. Energy detection provides maximum flexibility by not relying on any prior knowledge, but suffers from an SNR-wall due to noise uncertainty. Crosscorrelation of the outputs of two receiver paths is a technique to reduce the noise level of the total receiver, and hence improves the SNR. The reduction of the noise is limited by correlated noise originating from shared components near the antenna. In this paper we explore the use of a separate antenna for each receiver for crosscorrelation spectrum sensing. One immediate advantage is that due to the removal of the splitter, which was necessary to interface the single antenna to two receivers, the SNR improves, significantly reducing the required measurement time. A lot of the noise correlation can be removed, leading to a lower residual noise floor. The noise at each antenna will still be partially correlated due to mutual coupling, spatial noise correlation and man-made noise. We show that some signal power can be lost in the sensing process due to partial decorrelation of the signal at the two antennas. Fortunately, this seems to be a problem only in highly mobile environments, which makes the use of two-antenna crosscorrelation spectrum sensing an interesting solution towards more reliable energy detection.

This paper shows that the group delay of a delay circuit does not give sufficient information to predict the delay vs. frequency. A new criterion (fφ=0) is proposed that characterizes the delay variations over a specified frequency range. The mathematical derivation of fφ=0for a single delay block and a cascade of delay blocks is shown. As examples the criterion is applied to the design of an RC and LC delay block. Delay predictions based on fφ=0compared with simulation results, showing reasonable agreement.

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s.

This paper presents a novel way to efficiently implement parametric cells (P-cells). A narrow-band LNA is used as demonstration vehicle. In the P-cell, circuit parameters such as transistor size, bias condition and passive values are determined automatically for any given reachable target performance. To achieve both high accuracy and relatively high speed, a new iterative stepped approach is used with respect to speed and accuracy, starting with moderate-accuracy and fast optimization that yields the starting point for the next higher-accuracy and slower optimization step. The presented approach can be extended to other types of circuits.

This work describes a method of implementing a fully-integrated ultra-low power (ULP) radio for wireless sensor networks (WSN). This is achieved using a specific medium access control (MAC) protocol, employing a duty- cycled wake-up radio and a crystal-less clock generator, and an ad-hoc modulation scheme (Impulse Radio) with a bandwidth of 17.7 MHz in the 2.4 GHz - ISM band. The total average power consumption is expected to be less than 100 muW.

Many critical design trade-offs of the Class-E power amplifier (e.g power efficiency) are influenced by the switch on-resistance and the value of dc-feed drain inductance. In literature, the time-domain mathematical analyses of the Class-E power amplifier with finite dc-feed inductance assume zero switch on-resistance in order to alleviate the mathematical difficulties; resulting in non-optimum designs. We present analytical design equations in this paper for Class-E power amplifier taking into account both finite drain inductance and switch on-resistance. The analysis indicates the existence of infinitely many design equations; conclusions include: 1) Class-E conditions (e.g. zero voltage and zero slope) can be satisfied in the presence of switch-on resistance. 2) The drain-efficiency (η) of the Class-E power amplifier is upper limited for a certain operation frequency and transistor technology. 3) Using a finite dc-feed inductance instead of an RF-choke in a Class-E power amplifier can increaseηby≈ 30%.

This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when both are realized with current mode logic (CML) circuits and white noise is assumed. This is due to the factor that the shift register MPCG has no jitter accumulation from one clock phase to the other as in the DLL based MPCG. For N-phase clock generation, the shift register MPCG needs a reference clock with N times higher frequency and thus requires a VCO with higher frequency than the DLL counterpart. However, we can show that this does not lead to additional power consumption.

Nonlinearity and time-variance in radio frequency (RF) circuits leads to unwanted harmonics and intermodulation products, e.g. in power amplifiers and mixers. This paper reviews a recently proposed multipath polyphase circuit technique which can cancel such harmonics and intermodulation products. This will be illustrated using a power upconverter IC as an example. The upconverter works from DC to 2.4 GHz, and the multipath polyphase technique cleans its spectrum up to the 17th harmonic, keeping unwanted spurious responses more than 40dB below the carrier. The technique can also be useful for other applications, and some possible applications will be discussed.

CMOS radio receiver architectures, based on radio frequency (RF) sampling followed by discrete-time (D-T) signal processing via switched-capacitor circuits, have recently been proposed for dedicated radio standards. This paper explores the suitability of such D-T receivers for highly flexible software-defined radio (SDR) receivers. Via symbolic analysis and simulations the authors analyze the properties of D-T receivers, and show that at least three challenges exist to make a D-T receiver work for SDR: 1) the sampling clock frequency is related to the radio frequency, complicating baseband filter design; 2) a frequency-dependent phase shift is introduced by pseudo-quadrature and pseudo-differential sampling; 3) the conversion gain of a charge sampling front-end is strongly frequency-dependent. Compared to a mixer based radio receiver, extra costs are needed to solve these problems.

Crosstalk limits the achievable data rate of global on-chip interconnects on large CMOS ICs. This is especially the case, if low-swing signaling is used to reduce power consumption. Differential interconnects provide a solution for most crosstalk and noise sources, but not for neighbor-to-neighbor crosstalk in a data bus. This neighbor-to-neighbor crosstalk can be reduced with twists in the differential interconnect pairs. To reduce via resistance and metal layer use, we use as few twists as possible by placing only one twist in every even interconnect pair and only two twists in every odd interconnect pair. Analysis shows that there are optimal positions for the twists, which depend on the termination impedances of the interconnects. Theory and measurements on a 10-mm-long bus in 0.13-$\mu$m CMOS show that only one twist at 50% of the even interconnect pairs, two twists at 30% and 70% of the odd interconnect pairs, and both a low-ohmic source and a low-ohmic load impedance are very effective in mitigating the crosstalk.

Opamp-RC integrators built with linear resistors and capacitors can achieve very high linearity. By means of a switched resistor, tuning of the RC time-constant is possible via the duty-cycle of the clock controlling the switched resistor. This paper analyzes the effect of opamp slew rate limitations on the distortion of a switched-resistor lossy opamp-RC integrator. We show via analysis and simulations that the use of two sets of switched resistors instead of one relaxes the opamp slew rate requirements, and reduces the resulting distortion significantly.