This document describes a successful application of a semi-formal test generation technique to the verification of Direct Memory Access Controller (DMAC) of ST50, a new general purpose RISC microprocessor developed by STMicroelectronics and Hitachi. Like other memory-related devices, the DMA controller challenges formal techniques because of the state explosion problem. To cope with the challenge, abstraction mechanism is applied during test generation: several abstract models are created in order to verify different functional aspects of the design. We also propose a practical solution to overcome a temporal abstraction problem that arises when tests issued from an abstract model have to be applied during real design simulation.

This paper describes the first application of the Genevieve test generation methodology. The Genevieve approach uses semi-for-mal techniques derived from “model-checking” to generate test suites for specific behaviours of the design under test. An “interest-ing” behaviour is claimed to be unreachable. If a path from an ini-tial state to the state of interest does exist, a counter-example is generated. The sequence of states specifies a test for the desired behaviour.

Describes an industrial application of the Genevieve test generation methodology. The Genevieve approach uses formal techniques to generate test suites for specific design behaviour. The example, which is a part of the ST100 DSP, was chosen in order to highlight real life problems such as big data structures, complex control logic, and complex environments where it is difficult to determine how to drive the complete system to ensure a given behaviour in the unit under test.

One possible solution to the verification crisis is to bridge the gap between formal verification and simulation by using hybrid techniques.This paper presents a study of such a functional verification methodology that uses coverage of formal models to specify tests.This was applied to a modern superscalar microprocessor and the resulting tests were compared to tests generated using existing methods.The results showed some 50% improvement in transition coverage with less than a third the number of test instructions, demonstrating that hybrid techniques can significantly improve functional verification.1.

This paper summarizes the verification effort of a complex ASIC designated to be an “all in one” ISDN network router. This ASIC is unique because it actually consists of many independent components, called “cores ” (including the processor). The integration of these components onto one chip results in an ISOC (Integrated System On a Chip). The complexity of verifying an ISOC is virtually impossible without a proper methodology. This paper presents the methodology developed for verifying the router. In particular, the verification method as well as the tools that were built to execute this method are presented. Finally, a summary of the verification results is given.

This paper describes a system (AVPGEN) for generating tests (called architecture verification programs or AVP's) to check the conformance of processor designs to the specified architecture. To generate effective tests, AVPGEN uses novel concepts like symbolic execution and constraint solving, along with various biasing techniques. Unlike many earlier systems that make biased random choices, AVPGEN often chooses intermediate or final values and then solves for initial values that can lead to the desired values. A language called SIGL (symbolic instruction graph language) is provided in AVPGEN for the user to specify templates with symbolic constraints. The combination of user-specified constraints and the biasing functions is used to focus the tests on conditions that are interesting in that they are likely to activate various kinds of bugs. The system has been used successfully to debug many S/390 processors and is an integral part of the design process for these processors.>

Intelligent decision systems in time-invariant situations must be able to manipulate time-variant data and functions. The authors present an algorithm for the following dynamic computational problem: given a set of continuous functions, keep track efficiently of their order in their domain. The algorithm has time complexity of O(nlog/sub 2/n+K min(log/sub 2/n, log/sub 2/K)), where n is the number of functions and K is the total number of intersections between the functions. The solution provides for a convenient object-oriented view of the time-variant priority queue. Contrary to the abstract data type consisting of the array (data structure) and the associated utilities (push, pop), the time-variant priority queue maintains a private state as the data change.>