Proposes a novel model-reference robust speed control with a load torque estimator and feedforward compensation based on a neural network (NN) for induction motor drives with time delay. First, a two-layer neural network torque estimator (NNTE) is used to provide real-time identification for an unknown load torque disturbance. The backpropagation algorithm was used as the learning algorithm. In order to guarantee the system's convergence and to obtain faster NN learning ability, a Lyapunov function is also employed to find the bounds of the learning rate. Since the performance of the closed-loop controlled induction motor drive is influenced greatly by the presence of the inherent system dead-time during a wide range of operations, a dead-time compensator (DTC) and a model-reference-following controller (MRFC) using a NN proportional controller (NNPC) are proposed to enhance the robustness of the PI controller. A theoretical analysis, simulation and experimental results all demonstrate that the proposed model-reference robust control scheme can improve the performance of an induction motor drive with time delay, and can reduce its sensitivity to system parameter variations and load torque disturbances.

The maximal redundancy signed-digit (MAXSD) number system has the highest redundancy within the carry-absorbing signed-digit number system proposed by Avizienis in 1961. The digital values for radix R lie in [1-R, R-1]. Its compatibility with both standard nonredundant systems and binary arithmetic makes it an excellent choice far multiprecision arithmetic on binary machines. The representations for finite numbers are however nonunique and can even be unbounded in wordlength; this is resolved by algorithms for partial or complete conversion to standard nonredundant notation without explicit carry propagation.

In one iteration, Chen's algorithm for evaluating exponentials and logarithms advances by 2 bits on the average, yet may not advance at all. Analysis reveals that the no-advance situation actually paves the way for sizable advance in the next iteration, and the guaranteed advance, after a one iteration overhead, is one bit per iteration. Two new schemes raise the guaranteed advance to 1.5 bits per iteration, after a two-iteration overhead, while maintaining the original requirement of one stored constant per operand bit. Adopting as a figure of merit the following quantity Q = advance per iteration/memory words per operand bit for the steady-state iterations, the new schemes appears to be better than other methods heretofore proposed.

In multioperand additions p summands can be compressed into q summands by adding along the columns independently. For a given column Z with Boolean elements {zi}, this sum is Σrk2k, where rkequals a residue threshold function R(2k, 2k+1|Z), defined by the proposition R(t, m |Z) ≡ t ⩽ (Σzi) mod m. The hardware realization is particularly simple using symmetry-adapted READ-ONLY storage (ROS) array logic.

Using the formula A · B=[(A+ B)/2]2-[(A-B)/2]2, the binary multiplication problem is reducible to that of decomposing the square of P 0 · P1P2... Pkinto a sum of two or three quantities. For the eight-bit case, a study of the multiplication parallelogram suggests p2= R+ S+ T, where Pl and p8 appear only in R, and P2, P7 appear only in R and S. Each bit in T involves the ORing of no more than four terms, each involving no more than four Boolean variables. For a two-input adder, S and Tare combined into a six-variable problem, each bit may have up to 14 terms. The six-and four-bit problems are degenerate cases with R=0 and R= S=0, respectively.