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Sanping Wan

dblp:45/8406 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2025
0009-0005-0202-4633ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 56% Integrated circuit design · 44%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › analog and mixed-signal circuits
analog circuit design
0.912025
SMART: Graph Learning-Boosted Subcircuit Matching for Large-Scale Analog Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Electronic design automation › hardware verification and test › reverse engineering
subcircuit identification
0.912025
SMART: Graph Learning-Boosted Subcircuit Matching for Large-Scale Analog Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Electronic design automation › design automation tools
VLSI CAD
0.312025
SMART: Graph Learning-Boosted Subcircuit Matching for Large-Scale Analog Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025

Methods — techniques the papers use, named apart from their topics

radial matching · 0.9hypergraph neural network · 0.9graph learning · 0.9
YearPublicationVenuePosition
2025 SMART: Graph Learning-Boosted Subcircuit Matching for Large-Scale Analog Circuits
abstract
Subcircuit matching in a large-scale analog circuit is a fundamental problem in VLSI computer-aided design (CAD). Existing approaches suffer from a poor scalability issue for a large-scale analog circuit. In this article, we propose a graph learning-boosted subcircuit matching framework for large-scale analog circuits named SMART, consisting of two stages. In the first stage, we customize hypergraph neural networks to map circuit topology for embedding space. Then, coarse subcircuit recognition is directly performed in the embedding space by geometric relations between the query circuit and all candidate subcircuits within the target circuit. In the second stage, a radial matching method, including device attribute matching, connection relationship matching and uniqueness-based matching, is customized to perform fine matching and obtain matches between interconnections and devices in the query circuit and candidate subcircuits. Experimental results show our SMART can outperform state-of-the-art search-based method VF3 and learning-based method NeuroMatch, and achieve the fastest speed. Specifically, using our framework for subcircuit matching can achieve up to$135\times $speedup with slight accuracy loss, and up to$7\times $speedup while maintaining 100% accuracy.
Jindong Tu, Pengjia Li, Peng Xu 0052, Qianru Zhang, Sanping Wan, Yongsheng Sun, Bei Yu 0001, Tinghuan Chen
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.6
2024 Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization
abstract
Transistor aging leads to the deterioration of analog circuit performance over time. The worst aging degradation is used to evaluate the circuit reliability. It is extremely expensive to obtain it since several circuit stimuli need to be simulated. The worst degradation collection cost reduction brings an inaccurate training dataset when a machine learning (ML) model is used to fast perform the estimation. Motivated by the fact that there are many similar subcircuits in large-scale analog circuits, in this article we propose Wages to train an ML model on an inaccurate dataset for the worst aging degradation estimation via a domain generalization technique. A sampling-based method on the feature space of the transistor and its neighborhood subcircuit is developed to replace inaccurate labels. A consistent estimation for the worst degradation is enforced to update model parameters. Label updating and model updating are performed alternately to train an ML model on the inaccurate dataset. Experimental results on the very advanced 5 nm technology node show that our Wages can significantly reduce the label collection cost with a negligible estimation error for the worst aging degradations compared to the traditional methods.
Tinghuan Chen, Hao Geng, Qi Sun 0002, Sanping Wan, Yongsheng Sun, Huatao Yu, Bei Yu 0001
ACM Trans. Design Autom. Electr. Syst.4