Industrial control systems present numerous challenges from the communication systems perspective: clock synchronization, deterministic behavior, low latency, high reliability, flexibility, and scalability. These challenges are mostly solved with standard technologies over Ethernet, e.g., time-sensitive networking (TSN). As a research trend, it is expected that TSN will converge with wireless, leading to the Wireless TSN paradigm. Also, Wireless TSN is expected to be integrated with Ethernet TSN to create large-scale wired–wireless (Hybrid) TSN networks. The first step toward Hybrid TSN is the distribution of the clock reference from the wired to the wireless domain. In this article, we leverage existing Ethernet TSN and wireless technologies implementations (Wi-Fi and w-SHARP) and present two hardware architectures specifically engineered to enable the clock synchronization distribution among the network domains. The hardware architectures have been implemented over a system-on-chip field-programmable gate array platform. We demonstrate through several experiments that the implementation is able to fulfill the synchronization performance required by TSN.

The European Train Control System (ETCS) relies today on the 2nd generation cellular system GSM-R. GSM-R obsolescence has triggered the evolution of the current European Railway Traffic Management System (ERTMS) to the Future Railway Mobile Communication System (FRMCS), under development. FRMCS considers the use of several radio access technologies in parallel such as Wi-Fi, LTE, Satellite and 5G. Testing new communication systems along railway tracks is time and money consuming. Consequently, it is important to develop a zero-on-site-testing approach thanks to the development of emulation platforms. These platforms, combining hardware and software, are able to reproduce in laboratory real railway infrastructure behavior and scenarios. This paper presents the EMULRADIO4RAIL platforms, developed in the framework of Shift2Rail program and gives examples of results obtained.

Industrial automation systems that present strong real-time requirements have been traditionally implemented using wired networks. However, the prolific development of the wireless networks, and the important benefits derived from their use, have brought an increase in the introduction of the wireless networks as an extension of wired ones. Even so, the current wireless standards do not allow the coexistence with wired networks that present severe reliability and real-time requirements, such as those used in industrial control applications. In order to solve this problem, this paper presents a hybrid network with deterministic features, including a wired network with Time Sensitive Network (TSN) and a new Medium Access Control (MAC) wireless protocol for the wireless section. Moreover, this paper gives details about the bridge that has been developed for transmitting data between the two sections of the hybrid network in a deterministic way. The proposed approach has been implemented, and the measures in real hardware prove the fulfilment of the deterministic real-time requirements demanded by the hybrid network.

Press machine maintenance requires to incorporate cutting-edge technologies in the most critical elements for enhancing press and components robustness and functionality in order to facilitate proactive-predictive maintenance activities. In this work, a wireless torque sensor node has been designed, developed, tested and validated. This increases machines and components reliability reducing high costs caused by production downtimes with required maintenance repair operations. The development of this wireless torque sensor node improves maintenance strategies, monitoring and analysing non-intrusively the shaft status.

In this work a time-synchronized Wireless Sensor Network (WSN) has been designed and implemented for a realtime Structural Health Monitoring (SHM) system for trains. Channel measurements have been done in the first place on a real operational scenario, and obtained results have been used as inputs for the design of the physical layer of the WSN. A specific Time Division Multiple Access (TDMA) MAC layer and a synchronization algorithm have also been developed for allowing a deterministic data collection and synchronized sampling, which are critical aspects in SHM applications. Performance measurements of the WSN have also been done, which have shown maximum sampling synchronization jitter values within 1 μs for sensor nodes belonging the same base station, and maximum jitter values within 2 μs for nodes of different base stations.

This article presents a new solution for easing the development of reconfigurable applications using Field-Programable Gate Arrays (FPGAs). Namely, our Reliable Reconfigurable Real-Time Operating System (R3TOS) provides OS-like support for partially reconfigurable FPGAs. Unlike related works, R3TOS is founded on the basis of resource reusability and computation ephemerality. It makes intensive use of reconfiguration at very fine FPGA granularity, keeping the logic resources used only while performing computation and releasing them as soon as it is completed. To achieve this goal, R3TOS goes beyond the traditional approach of using reconfigurable slots with fixed boundaries interconnected by means of a static communication infrastructure. Instead, R3TOS approaches a static route-free system where nearly everything is reconfigurable. The tasks are concatenated to form a computation chain through which partial results naturally flow, and data are exchanged among remotely located tasks using FPGA’s reconfiguration mechanism or by means of “removable” routing circuits. In this article, we describe the R3TOS microkernel architecture as well as its hardware abstraction services and programming interface. Notably, the article presents a set of novel circuits and mechanisms to overcome the limitations and exploit the opportunities of Xilinx reconfigurable technology in the scope of hardware multitasking and dependability.

Despite the clear potential of FPGAs to push the current power wall beyond what is possible with general-purpose processors, as well as to meet ever more exigent reliability requirements, the lack of standard tools and interfaces to develop reconfigurable applications limits FPGAs' user base and makes their programming not productive. R3TOS is our contribution to tackle this problem. It provides systematic OS support for FPGAs, allowing the exploitation of some of the most advanced capabilities of FPGA technology by inexperienced users. What makes R3TOS special is its nonconventional way of exploiting on-chip resources: These are used indistinguishably for carrying out either computation or communication tasks at different times. Indeed, R3TOS does not rely on any static infrastructure apart from its own core circuitry, which is constrained to a specific region within the FPGA where it is implemented. Thus, the rest of the device is kept free of obstacles, with the spare resources ready to be used as and whenever needed. At runtime, the hardware tasks are scheduled and allocated with the dual objective of improving computation density and circumventing damaged resources on the FPGA.

This paper presents the implementation of several data coding functions used in Software Defined Radios, on R3TOS: a Reliable, Reconfigurable and Real-Time Operating System. The latter offers efficient high performance computing on FPGAs as well as protection against emerging faults, hence making it a perfect candidate for the implementation of SDRs. In particular, R3TOS' ICAP-based Inter-task Communication Infrastructure (I2CI) has been used for data feeding and collection from coding functions, while a task context saving and restoration procedure, and a fast function parameterization system have been developed in order to improve system performance. The design of the data coding functions has been carried out using Xilinx's rapid prototyping tool System Generator in order to ease their development.

This paper presents the details of a novel technique which allows for the implementation and execution of completely relocatable hardware tasks onto dynamically reconfigurable FPGAs. Our novel technique harnesses the internal configuration access port (ICAP) for inter-task communication and synchronization, leading to very little logic overheads. The advantages of this technique include fault-tolerance, as tasks could be relocated freely on the fabric to circumvent damaged resources, and high performance, due to better exploitation of the logic fabric. The work is part of a larger effort in our group which aims to build a fully operational dynamically reconfigurable computer which would satisfy the often conflicting requirements of high performance, fault-tolerance and high level programming.