EDBT 2026 Demo / reviewers in the wild / expert
Donggu Im
dblp:46/10820
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4ranked-venue papers
0as first author
4since 2021 · last 2026
0000-0003-2892-6254ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 4 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | A Handgrip-Responsive mmWave Phased Array Antenna-PA Module With Antenna-Based Capacitive Sensor for EIRP Recovery via Adaptive Current RedistributionabstractThis paper presents a 5G/6G millimeter-wave (mmWave) phased array antenna-power amplifier module that recovers the effective isotropic radiated power (EIRP) during a user’s handgrip in mobile devices. A sentenna device, which combines a capacitive sensor and an antenna to enable both wireless communication and handgrip detection, is designed and utilized to distinguish between antenna elements blocked by a user’s hand and those unblocked within the phased-array system, without using external sensors such as radar sensors. Based on handgrip information from the sentenna devices, current to the front-end circuits of blocked antenna units is cut off and redistributed to those of unblocked units. In the absence of handgrip detection and current redistribution (CR) functions, the measured EIRP of the$1\times 4$phased array sentenna system drops from + 31.4 dBm to + 22.4 dBm when up to three sentenna units are blocked. In contrast, with these functions enabled, the worst-case EIRP degradation is limited to + 27.4 dBm, effectively mitigating up to 5 dB of performance loss. Notably, this EIRP recovery is achieved while also improving the output-referred third-order intercept point (OIP3). Gyeore Lee, Jeong-Ung Yoo, Hae-Won Son, Jung-Mu Kim, Wooyeol Choi 0001, Donggu Im |
IEEE Trans. Circuits Syst. I Regul. Pap. | 7 |
| 2024 | A Sub-GHz/2.4 GHz Highly Selective Reconfigurable RF Front-End Employing an N-Path Complementary Balun-LNA and Linearized RF-to-BB Current-Reuse MixerabstractA sub-GHz/2.4 GHz highly selective reconfigurable RF front-end employing$N$-path complementary balun-LNA and linearized RF-to-BB current-reuse (CR) mixer is proposed to implement internet-of-things (IoT) devices supporting short- and long-range wireless connectivity technologies. The proposed balun-LNA is built based on an active feedback common-source (CS) amplifier with a common-gate common-source (CGCS) balun load. A complementary version is devised to avoid a severe voltage drop across the resistor load attaining sufficiently high gain and increased effective transconductance without additional current consumption. In addition, an 8-path notch filter is added at a feedback path to improve LNA selectivity in sub-GHz. At 2.4 GHz, an inductive source degenerated LNA (ISDLNA) is used to achieve low noise figure (NF). The proposed RF-to-BB current-reuse mixer employed a second-order-intermodulation (IM2) injection technique for the linearization of the RF front-end. The IM2 injection technique improves linearity by generating the in-phase fundamental signal and out-of-phase third-order-intermodulation (IM3) signal, compared to the passive mixer output. The auxiliary path for the linearization is designed to consume ultra-low power by employing a newly proposed current-reuse-based differential IM2 generator, passive multiplier, and current-steering-based summing stage. As a result, the proposed RF-to-BB CR mixer alleviates the loading effect for the balun-LNA while achieving better gain, NF, and linearity with low power consumption. In measurement, the proposed front-end achieved the conversion gain of 50.5 ~ 44.4 dB and 39.4 dB and double-sideband noise figure (NFDSB) of 4.4 ~ 5.7 dB and 5.3 dB, respectively, in sub-GHz and 2.4 GHz. It also achieved in-band and out-of-band input-referred third-order intercept point (IIP3) from −18.0 to −15.2 dBm and from −0.4 to −2.6 dBm in sub-GHz and, the in-band IIP3 of −15.0 dBm at 2.4 GHz. The chip area of the proposed RF front-end core was less than 1.3 mm2 excluding the measurement buffer and I/O PADs. Dongmyeong Kim, Ignacio Llamas-Garro, Donggu Im |
IEEE Trans. Circuits Syst. I Regul. Pap. | 4 |
| 2022 | A Reconfigurable Balun-LNA and Tunable Filter With Frequency-Optimized Harmonic Rejection for Sub-GHz and 2.4 GHz IoT ReceiversabstractA CMOS reconfigurable balun-LNA and tunable filter is proposed for sub-GHz and 2.4 GHz IoT applications. The core of the LNA gain stage is composed of two cascaded inverters for the single-to-differential conversion, and the additional inverter is placed in the feedback path for the implementation of the active feedback. In the sub-GHz band, it operates as an active feedback LNA by enabling all inverter stages. At the narrow 2.4 GHz band, it operates as an inductive source degenerated LNA (ISDLNA) with a minimum noise figure (NF) by disabling the inverter in the feedback path. In order to suppress the unwanted local oscillator (LO) harmonic mixing in the sub-GHz band and provide the frequency-optimized harmonic rejection ratio (HRR), a reconfigurable Sallen-Key (SK) filter-based$4^{\mathbf {th}}$-order tunable filter is proposed on the basis of the modified super source follower (SSF) with enhanced loop gain. It covers the entire VHF band with a smaller capacitance tuning ratio by switching the polarity of the output of the modified SSF. Compared to previous works, this work provides the largest tuning range from 50 MHz to 700 MHz without splitting individually optimized circuits corresponding to each frequency band and using no external board components. This is the first suggestion of a fully integrated SK filter-based tunable filter to cover VHF/UHF bands through a hardware re-configurability without increasing the tuning ratio of the switched capacitor array, while providing an optimum HRR performance for corresponding operating frequencies in conjunction with harmonic rejection mixer (HRM). In addition, it proposes a hardware efficient re-configurable balun-LNA to operate as a wideband feedback LNA at sub-GHz and a narrowband ISDLNA at 2.4 GHz without the use of external input matching circuits. In the measurement, the proposed front-end achieves an average power gain ($\text{S}_{{21}}$) of 25.9 dB, NF of$>\!\!\!-12.8$dBm over the tuning range from 50 MHz to 700MHz. The proposed tunable filter shows the frequency-optimized HRR from 10 dBc to 26 dBc over the tuning range while greatly reducing a silicon area. At 2.4 GHz band, it shows$\text{S}_{{21}}$of 14.7 dB, NF of 3.2 dB, and in-band IIP3 of −4.5 dBm. The die area of the proposed circuit, excluding I/O PADs and the measurement output buffer, is less than 2.0 mm2. The power consumption of the front-end working at sub-GHz and 2.4 GHz bands is 33.6 mW and 5.1 mW respectively. Donggu Im |
IEEE Trans. Circuits Syst. I Regul. Pap. | 2 |
| 2021 | A Reconfigurable Passive Mixer-Based Sub-GHz Receiver Front-End for Fast Spectrum Sensing FunctionalityabstractA reconfigurable parallel mixing subharmonic mixer (SHM)-based time-interleaved RF channelizer is proposed for fast spectrum sensing. The reconfigurable mixer operates as a double-balanced mixer (DBM), a double-balanced mixer with harmonic rejection (DBM&HR), and an SHM. In contrast to conventional spectrum sensing receivers to detect RF frequency bands by sweeping local oscillator (LO) frequencies, the proposed receiver scans multiple frequency bands quickly through mode change of the reconfigurable mixer. The LO generation circuit employs a voltage subtractor-based phase adder and provides highly accurate 25% duty-cycle octet-phase LO signals. The front-end implements a high LO harmonic rejection ratio (HRR) in order to avoid signal corruption by LO harmonic mixing during spectrum sensing. In experiments, the proposed receiver achieves-35.8 dBm in-band input-referred third-order intercept point (IIP3), > -22.3 dBm out-of-band IIP3, and an average 3rdLO HRR of 43 dB over 300-800 MHz in DBM&HR mode. Over 600-1200 MHz in SHM mode, it shows >31.8 dB conversion gain,-30.9 dBm in-band IIP3, and > -20.1 dBm out-of-band IIP3. The switching time between DBH&HR and SHM modes is approximately 135 ns. The power dissipation is 24.7 mW from a 1.2 V supply voltage. Seongjin Bae, Dongmyeong Kim, Ilku Nam, Donggu Im |
IEEE Trans. Circuits Syst. I Regul. Pap. | 5 |