The software environment of ULTIMATE has been described. Distributed processing by three-layer processors and parallelism of per-pin controllers make it possible to attain high-speed and flexible data processing. Since ULTIMATE is connected to a host computer as a terminal device, users can operate it in the same environment as CAD-application programs. Operationability is thus greatly improved compared with conventional stand-alone testers. This arrangement also results in a powerful fault analysis tool in cooperation with an electron beam tester.>

The prototype VLSI test system ULTIMATE has a 1024-pin capability at 500-MHz test rate and a timing accuracy of +or-50 ps. A novel packaging method improves signal quality, heat removal, and cost. ULTIMATE's compact water cooled frame and thermal conduction elements enable 10001 W/L power consumption at a packing density of 270 chips/L.>

Technologies needed for constructing ULTIMATE, including an 8-ps-resolution timing generator, a formatter with a real-time waveform control function, a 2.5-ps-resolution standard comparator, and a miniaturized 3-GHz 59-pole channel selector are described. Almost all the pin-electronics hardware has been integrated on twelve kinds of LSIs, eight of which are 2.5 K-gate and 400-gate ultrahigh-speed bipolar gate arrays. ULTIMATE realizes +or-55-ps overall timing accuracy by the timing calibration method which combines a standard comparator-based method and a TDR (time-domain reflectometry)-based method.>

The current status of semiconductor device simulation at NTT is described. Device simulators at NTT are classified into two categories. One is the conventional macroscopic approach and the other is microscopic particle analysis using a Monte Carlo method. In this paper, these simulators are introduced together with the more interesting results. Through these examples, it is demonstrated that the device simulation takes an important role for accurate modeling of semiconductor devices. This report also concludes that the choosing the best simulation program for a given problem is the key to obtain effectively an accurate solution.

A new hierarchical top-down layout design system for custom VLSIs has been developed. A top-down global route assignment process reduces the redundant wiring area. Routing in a single path over the whole chip enables efficient chip area use.