Criteria and methods for accurately modeling LSI/VLSI interconnect lines at various high-frequency ranges are discussed. The Elmore-Sakurai RC model for delay time is verified for frequencies of tens to low hundreds of MHz. The inductance effect is then analyzed for frequencies from high tens to low hundreds of MHz to 50 GHz. General and special transfer functions are analyzed and plotted. The skin-effect-caused frequency dependence of line resistance and inductance are considered. Finally, the impulse response function is derived from inverting the transfer function, and simplified for efficient computerisation of the transient response of an interconnect line at very high frequencies. The models are verified to the exact fit using a network analyzer and digitizing oscilloscope in a magnetically and electrically shielded environment, measuring the S-parameters (amplitude of transfer function), phase, and transient responses.>

A generic integrated optoelectronic-to-VLSI packaging technology using silicon substrate and etched silicon optical submount has been developed and demonstrated. The miniature silicon submount that interfaces optical fiber with the optoelectronic component and the silicon substrate containing VLSI circuits is fabricated with double-sided nonplanar photolithography and anisotropic etching techniques. The advantages of this technology are: ability to interface optical information and circuits with VLSI in a single package; precision controlled capacitive, resistive, and inductive loading; minimized distance between optoelectronic components and electronic ICs, and between decoupling capacitors and active circuits; self-aligned fiber insertion; and highly automated manufacturing. These advantages translate to higher functional density and performance at a lower cost than conventional optoelectronic packaging technologies.>

A 32-b floating-point digital signal processor IC is integrated with eight 16 K*4-b SRAM chips on a silicon substrate, thus minimizing the parasitic loading to the processor buffer and enabling zero-wait-state access of the full 64-kB of memory. The module is rated at 25 MHz up to 125 degrees C and 70 MHz at liquid nitrogen temperature. A large percentage of modules operate up to 40 MHz at room temperature. The assembly is packaged in a standard 133 pin PGA ceramic package identical in size and footprint with the package used for the signal processor IC alone. This multichip packaging approach has significant potential for improving system performance and reducing cost. The signal processing module described was designed as a vehicle for such demonstration. The electrical analysis and design criteria, physical packaging, and testing strategies are discussed.>