In this paper, a self-routing permutation network based on a binary radix sorting network has been proposed. It has O(log/sup 2/ n) propagation delay and O(n log/sup 2/ n) hardware complexity with bit-parallel input. The hardware complexity can be reduced to O(n log n) with bit-serial input. The binary radix sorting network is recursively constructed by log n stages of bit sorting networks. The bit sorting network is then constructed by a proposed self-routing reverse banyan network. It has O(log n) propagation delay and O(n log n) hardware complexity. The proposed reverse banyan network has been fully verified by Verilog Hardware Description Language in logical level. The VLSI design of its switching elements is simple and regular.