As modern field-programmable gate arrays (FPGA) enable high computing performance and efficiency, their programming with low-level hardware description languages is time-consuming and remains a major obstacle to their adoption. High-level synthesis compilers are able to produce register-transfer-level (RTL) designs from C/C++ algorithmic descriptions, but despite allowing significant design-time improvements, these tools are not always able to generate hardware designs that compare to handmade RTL designs. In this article, we consider synthesis from an intermediate-level (IL) language that allows the description of algorithmic state machines handling connections between streaming sources and sinks. However, the interconnection of streaming sources and sinks can lead to cyclic combinational relations, resulting in undesirable behaviors or un-synthesizable designs. We propose a functional-level methodology to automate the resolution of such cyclic relations into acyclic combinational functions. The proposed IL synthesis methodology has been applied to the design of pipelined floating-point cores. The results obtained show how the proposed IL methodology can simplify the description of pipelined architectures while enabling performances that are close to those achievable through an RTL design methodology.

Decades of research in the field of high level hardware description now result in tools that are able to automatically transform C/C++ constructs into highly optimized parallel and pipelined architectures. Such approaches work fine when the control flow is a priory known since the computation results in a large dataflow graph that can be mapped into the available operators. Nevertheless, some applications have a control flow that is highly dependant on the data. This paper focuses on the hardware implementation of such applications and presents a high level synthesis methodology applied to a Hardware Description Language (HDL) in which assignments correspond to self-synchronized connections between predefined data streaming sources and sinks. A data transfer occurs over an established connection when both source and sink are ready, according to their synchronization interfaces. Founded on a high-level communicating FSM programming model, the language allows the user to describe and dynamically modify streaming architectures exploiting spatial and temporal parallelism. Our compiler attempts to maximize the number of transfers at each clock cycle and automatically fixes the potential combinatorial loops induced by the dynamic connection of dependant sources and sinks. The methodology is applied to the synthesis of a pipelined floating point accumulator using the Delayed-Buffering (DB) reduction method. The results we obtain are similar to state-of-the-art dedicated architectures but require much less design time and expertise.

Field-Programmable-Gate-Arrays are used increasingly to speed up applications in various fields of science. But as modern digital designs integrate hundreds of interconnected processing and memory units, the need for a higher level of abstraction to handle their descriptions is indisputable. This paper presents a beyond-RTL concurrent hardware description language that combines both Finite-State Machine (FSM) and constraint programming paradigms. At the featured level of abstraction, the user describes dynamic connections between data sources and sinks that may not always be ready to send or receive data tokens. The high-level description methodology enables a comprehensible description of behaviors such as data transfer synchronization, exclusivity, priority and constrained scheduling by the means of logical-implication rules constraining the data transfers authorizations. Dynamically connecting resources with potential combinatorial dependencies may lead to instability or deadlock. Such situations are automatically detected and fixed by the proposed compiler that generates a dedicated control-circuit optimizing the number of transfers that can be authorized at each clock cycle. The proposed design automation methodology is applied to the problem of deeply-pipelined vector reduction. A pipelined floating point accumulator and a matrix multiplication circuits are described with a few lines of code and automatically compiled into an FPGA. Results show that the synthesis results are comparable to those obtained with hand-written RTL but with much lower effort and time.

As the complexity of modern digital systems continues to increase exponentially, the need for beyondRTL design methodologies is growing as well. In this paper, we propose a high-level hardware description language that allows the user to dynamically modify and constrain the connections between data token sources and sinks. Actual transfers occur when both sources and sinks are ready to proceed, according to different predefined synchronization protocols. At this level of abstraction, both FSM programming and constraint programming paradigms are combined to enhance the user's ability to describe and exploit fine-grain parallelismin control-intensive hardware designs. The proposed hardware description methodology is applied to the description of two hardware implementations of the QuickSort algorithm, using pipelined memory and comparator components.

This paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable FPGA. The TDC architecture is based on the Vernier method using two ring oscillators with slightly different frequencies. The proposed oscillators can be calibrated with picoseconds resolution by taking advantage of partial reconfiguration, and moreover recalibrated over time. The results obtained on a Xilinx Virtex-II Pro FPGA show that the proposed TDC implementation can achieve unprecedented resolutions (on FPGA) as low as 5ps and precisions up to 25ps.

This paper presents a novel application specific instruction set processor specialized for block motion estimation. The proposed architecture includes an efficient register file system in terms of data reuse and parallel processing. Performances and area costs are presented for different levels of parallelism and register file dimensions. Various FPGA implementations of the architecture are further studied in order to present the most important factors affecting performance and hardware resource utilization. The proposed instruction extension block architecture enables acceleration by 3 orders of magnitude for full-search block matching algorithms.