Monolithic inter-tier vias (MIVs) in monolithic 3-D integrated circuits (M3D ICs) enables massive vertical integration. However, MIVs are more susceptible to defects due to high integration density and complex manufacturing processes. Existing MIV test techniques can effectively detect and locate MIV faults, but diagnosable fault types are limited. We propose a novel fault diagnosis method based on signal transmission performance analysis. This method can diagnose more fault types, including resistive open, hard open, short, and leakage faults. In the proposed solution, fault diagnosis can be carried out by comprehensively monitoring voltage and delay characteristics of MIVs. The effectiveness of fault diagnosis is verified through high speed simulation program with integrated circuit emphasis (HSPICE) simulations. We also perform Monte Carlo simulations to prove that the proposed method has high robustness even in the case of process variations. Experimental results show that the proposed method has low hardware overhead while ensuring high diagnostic resolution.

Monolithic 3D integration realizes the vertical interconnection between adjacent layers by using nanoscale monolithic inter-tier vias (MIVs). However, MIVs are particularly vulnerable to defects due to high integration density and substantial scaling of the inter-layer dielectric. We propose a novel test method to detect open, short, and leakage faults in MIVs. Since the MIV defect will change its electrical characteristics, this method can test the MIV by identifying the voltage range divided according to different MIV faults. The effectiveness of fault detection is verified through HSPICE simulations. We also perform Monte Carlo simulations to prove the testability of the proposed method even in the case of process variations. Experimental results show that the proposed method has high detection precision while ensuring low hardware overhead.

Anomaly detection is a crucial matter to ensure the spacecraft stability. During the spacecraft operation, sensors and controllers generate a large volume of multidimensional time series telemetry data with long periodicity, and one key point to detect the anomaly inside the spacecraft timely and precisely is to extract essential features from the sheer amount of telemetry data. However, great challenges exist owing to the complex coupling relationships and the temporal characteristics inside the telemetry data. To address this issue, we propose a novel approach called maximum information coefficient attention graph network (MAG). The basic frame is a graph neural network, which utilizes embedding vectors to describe the intrinsic properties of each dimension, correlation analysis to investigate long-term dependencies, an attention mechanism to determine short-term interactions among dimensions, and long short term memory (LSTM) to extract temporal features. The fusion of these modules through a graph neural network results in the construction of the MAG model, allowing for a comprehensive analysis of complex variable relationships and temporal characteristics leading to successful detection of various types of anomalies. Since telemetry data has heterogeneous characteristics, we adapt the loss function and design an unsupervised anomaly scoring method suitable for MAG. To verify the effectiveness of the proposed algorithm, we conducted experiments using two publicly and two new available spacecraft telemetry datasets, and the results demonstrate that our algorithm is more efficient and accurate in detecting spacecraft data anomalies than several other state-of-the-art methods.

Monolithic 3-D integrated circuits (M3D ICs) have a higher integration and better performance compared to 3-D ICs based on through-silicon vias. However, high integration density and substantial scaling of the interlayer dielectric (ILD) make M3D ICs extremely prone to occur process defects. In fact, defects such as voids often occur in the bonding process of M3D ICs. Therefore, ILD void detection is necessary in order to achieve high yield for M3D ICs. In this article, an ILD void detection method based on switched capacitors is proposed. Since voids affect the equivalent capacitance of logic gates above the ILD, voids can be discovered by measuring the gate-level equivalent capacitance. And the value of the capacitance can reflect severity of the void. The effectiveness and accuracy of the proposed method are verified by HSPICE simulations. For M3D ICs with the 22-nm process, the minimum capacitance variation identified by this method is 3.355 fF under process variation. And this means nanoscale voids can be detected by the proposed method.

During the manufacturing process of three-dimensional integrated circuits (3-D ICs), many defects may occur in through-silicon vias (TSVs). These defects affect the integrity of the signal passing through TSVs, therefore detecting these defects in the early production stage is crucial. This article proposed a built-in-self-test (BIST) method with a simple test structure and easily implemented fault detection process. Due to the fact that the defects in TSVs influence the charge/discharge speed of TSVs’ equivalent capacitance, a weak current source is designed as the central part of the proposed test structure, which can measure the TSVs’ charge/discharge speed and quantify it using digital values. The effectiveness and robustness of the proposed method is validated by HSPICE simulation. The minimum measurable fault, test time, and test circuit area are also assessed in this article. The simulation results show that the method this article proposed can detect weaker faults, compared with the traditional test methods.

The aluminum electrolytic capacitor (AEC) plays a key role in power electronic converter, but it is the most vulnerable component in the DC-DC converter. Throughout its short lifespan, the equivalent series resistance (ESR) will increase with the AEC aging. Therefore, it is important to monitor the ESR for ensuring the normal operation of a DC-DC converter. For a boost converter operating on discontinuous conduction mode and continuous conduction mode, an online noninvasive ESR estimation method was proposed in this paper. Based on the expression derivation of the output voltage, the ESR can be estimated by sampling the output ripple voltage at three specific moments. The proposed method is a noninvasive method, which does not require the current sensors. This method can be used in the discontinuous conduction mode and critical conduction mode. The simulation results verify the effectiveness of the proposed method.

As semiconductor technology develops, three-dimensions integrated circuits (3-D ICs) is thought as a viable solution to further improve the performance of ICs. Throughsilicon-vias (TSVs) are the most important device in 3-D ICs. Therefore, TSVs testing is a very critical flow in 3-D ICs manufacturing. A new pre-bond TSVs test solution is proposed in this paper. The new test structure includes an improved ring oscillator and a voltage-divider structure. Compared with conventional TSV test structure, the output of new test structure is more sensitive to TSV faults. We prove the effectiveness of the new test structure by HSPICE simulation.

Carrier and symbol synchronization are the key prerequisite for the accurate reception of the Quadrature Phase Shift Keying (QPSK) signal. The traditional synchronization methods have some intrinsic problems, such as slow speed, difficult to design the coefficients for the loop filter. In this paper, an adaptive carrier and symbol joint synchronization method is proposed, which applies the idea of segmented synchronization. The proposed approach divides the synchronization process into two stages: coarse stage and fine stage. In the coarse stage, loop filters with large bandwidth are used to fast capture the range of the carrier frequency offset (CFO) and symbol timing offset (STO). While, in the fine stage, filters with small bandwidth are adopted to accurately calculate and track the offsets. In addition, the proposed method can track the variation of the offsets dynamically, thus, it can adaptively identify the synchronization status and select the suitable structure and coefficients for different synchronization stages. Simulation results show that, compared with the traditional joint method, our proposed method can take into account the synchronization speed and stability simultaneously, and the speed and stability can be increased by 1.2 times and 21.77%, respectively, when the CFO is 1.5% of the symbol rate and STO is 0.5% of the symbol rate. Our proposed method can be used to solve the synchronization problem for the harsh environment, especially for the field of satellite communications, which has extremely large frequency and timing offsets.

In this paper, we propose a novel post-bond through-silicon via (TSV) test method for post-bond TSV manufacture test. The proposed method can measure the RGC parameters of TSVs using switched-capacitor circuits and calibration method and detect TSV leakage fault, open fault, high-resistance fault, and delay fault based on the measured RGC parameters. The test process has a high resolution and is robust. The fault-detection effectiveness is evaluated via HSPICE simulations. The results of the TSV capacitance measurement have a relative error within 1%, the TSV resistance measurement results have a relative error within 5%, and the TSV conductance measurement results have a relative error within 8.5%. We also perform an Monte Carlo simulation to prove that even under process variation, the proposed method can obtain a TSV capacitance within an absolute error of ±3 fF, obtain a TSV resistance with a relative error of no more than 18.4%, and obtain a TSV conductance of less than 100 ${\mu \Omega }^{{-1}}$ with a relative error of no more than 13%.

During the 3-D ICs manufacturing process, TSVs are susceptible to undergo different faults. Among these faults, the leakage fault is one of the most common cases. In this paper, a new test structure based on the improved ring oscillator circuit is proposed to detect the TSV leakage fault. An accurate TSV leakage fault model extracted from three-dimensional full-wave simulation is adopted in the test structure. HSPICE Monte Carlo simulation shows that the proposed test structure can detect the weak leakage faults with no less than 0.2025um2 pin-hole area, which is a larger coverage compared with the traditional test structure.

As an integrated circuit (IC) technology develops, 3-D stacked ICs based on through-silicon-via (TSV) technology have attracted the attention of the semiconductor industry. In 3-D stacked ICs, the TSV forms signal paths that vertically connect different ICs. The signal integrity largely depends on the quality of the TSV. A key challenge to the commercial viability of 3-D ICs is developing a method of accomplishing prebond TSV tests. To address this problem, we propose a prebond TSV test method with easily applied Design for Testability (DfT) structures and a simple fault-detection process. The proposed method is based on switched-capacitor circuits, which can detect TSV leakage faults, open faults, and high-resistance faults with high resolution. The fault-detection effectiveness is evaluated via HSPICE simulations. We also present an overall assessment of the test resolution, test time, and DfT area cost.

In this paper, we propose a test data compression method, which combines the advantages of dictionary-based compression and bit mask-based compression. We present a kind of Unfixed-Based Index (UBI), which uses shorter indexes to represent the slices with higher occurrence frequency, while uses longer indexes to represent the slices with lower occurrence frequency. Then, we adopt efficient bit mask and Max-Degree based Clique Partition Algorithm (MD-CPA) to create as many compatible slices as possible. Moreover, we propose a new Variable Prefix Dual-Run-Length (VPDRL) code to compress the un-compatible slices. To demonstrate the usefulness of our approach, we have applied our scheme on ISCAS'89 benchmarks and compared our results with existing compression techniques. Our algorithm outperforms existing dictionary-based compression and other compression methods.