In this article, a power-on-reset (POR) circuit with accurate trigger-point voltage and ultralow typical quiescent current for emerging nonvolatile memory (NVM) is presented. To keep the trigger-point voltage from the effect of process, voltage, and temperature (PVT) and supply ramp rate variations, low-cost current generators and a current comparator are adopted with brown-out detection (BOD). A protection circuit is utilized for correct operations in different BOD events. Meanwhile, delay blocks are utilized to generate reliable pulse signals that are less influenced by temperature and supply ramp rate. The simulation results show that the trigger-point voltage is 2.08 V with a temperature coefficient (TC) of 81.8 ppm/$^{\circ}$C and a deviation to the ramp time of 9.91% for a wide ramp time range from 10$\mu $s to dc. In addition, the reset duration time of the POR pulse is also reliable. The proposed POR circuit designed in the 55-nm CMOS process consumes only 0.65-nA typical quiescent current and 59$\times$146$\mu $m area, which is suitable for emerging NVM systems.

In this article, a low-cost quadruple-node-upsets resilient latch (LCQRL) design is proposed. To meet the high-reliability demands of safety-critical applications, the latch integrates nine soft-error-interceptive modules (SIMs) to form robust feedback loops, ensuring complete resilience to quadruple-node upsets (QNUs). Each Sim comprises ten CMOS transistors and a clocked inverter. Notably, C-element (CE) and dual interlocked storage cell (DICE) modules are not employed in this circuit, resulting in a small area and low power consumption. The simulation results verify the complete QNU self-recoverability and cost-effectiveness of this design. Compared with the existing radiation-hardened QNU resilient latches, the LCQRL latch demonstrates significant improvements in area, power consumption, and area-power–delay product (APDP) by 47.8%, 63%, and 75.5%, respectively. Furthermore, it exhibits low sensitivity to process, voltage, and temperature (PVT) variations.

Since spiking neural networks (SNNs) can effectively simulate the information processing mechanism of the biological cortex, they are expected to bridge the gap between neuroscience and machine learning. The hardware simulation of large-scale SNNs requires a simple and versatile silicon neuron model framework. In this article, a spiking neuron circuit as the core device of SNNs is presented. The proposed neuron circuit can mimic the dynamics of different types of biological neurons by adjusting the bias voltage. In order to facilitate the implementation of the spiking neuron circuit based on complementary metal-oxide-semiconductor (CMOS) and reduce the overhead of the circuit area, a modified Mihalas–Niebur (MN) mathematical model is adopted. The improved MN model is biologically plausible and can still successfully display all dynamic behaviors observed in biology. The function of the proposed neuron circuit has been verified by the phase diagram analysis method. The simulation results show the designed neuron circuit can successfully replicate 15 of the 20 firing patterns exhibited by the biological cortex, which proves that the neuron can act as a universal spiking neuron in very large-scale integrated circuit (VLSI) neuromorphic networks.

As one of the most promising candidates for nonvolatile memory, phase change memory (PCM) technology has shown great performance advantages in market applications. However, the conventional test methods have not kept pace with the development. In this article, focusing on specific PCM faults and others, an enhanced march test algorithm is proposed to achieve 100% fault coverage and diagnostic accuracy in bit-oriented PCM. The proposed algorithm is then converted for word-oriented PCM and equipped with capability to detect potential intraword impact. In addition, to reduce the dependence of memory test on the external devices, a novel storage scheme of fault information is devised. Through the modeling and simulation in C-language, this method is proven to improve the probability of finding the predefined fault-free regions in the tested memory. Finally, combining the enhanced test algorithm and the novel storage scheme, a built-in self-test (BIST) march test scheme is proposed, realizing the independent test of PCM without any external equipment. By comparison, the result of experiments, which are performed with C-language, proves that the proposed test scheme not only increases the fault coverage and diagnostic accuracy, but also reduces the additional area overhead.