Even simple models of interactions between the immune system and pathogens involve nonlinearity, stochastics, and feedback in analog circuits. Here, we show that even the simplest and most fundamental interactions involving the innate immune system, the adaptive immune system, and a pathogenic population in a 3-state dynamical system can lead to six discrete behaviors. These distinct behaviors may be categorized as the initial pathogenic disease state leading to a i) Cure; ii) Death; iii) Resurgence; iv) Chronic Condition; v) Autoimmune Behavior; or vi) Erratic Chaos-like Behavior. We show that the inactivation of strong positive feedback in the immune system when pathogenic populations have subsided is important in ensuring that its strength is not the enemy of calmness. Hence, appropriate sensitivity and reactivity to pathogen of the innate and/or adaptive immune system's positive-feedback loops are important in avoiding death, promoting a cure, and in suppressing subsequent autoimmune behavior. Stochastic viral replication at the edge of instability can lead to cure or non-cure behaviors, depending on chance. We show that feedback-loop visualizations and time-dependent small-signal eigen-circuit analyses of nonlinear dynamics provide insight into identifying a reduced set of parameters that determine stability, phase transitions, and final behavior.

This paper describes an adaptive noise generator circuit suitable for on-chip simulations of stochastic chemical kinetics. The circuit uses amplified BJT white noise and adaptive low-pass filtering to emulate the power spectrum and autocorrelation of random telegraph signals (RTS) with Poisson-distributed level transitions. A current-mode implementation in the AMS 0.35$\mu \text{m}$BiCMOS process shows excellent agreement with theoretical results from the Gillespie stochastic simulation algorithm over a 60 dB range in mean current levels (modeling molecule count numbers). The circuit has an estimated layout area of 0.032 mm2 and typically consumes 400$\mu \text{A}$, which are 73% and 50% less, respectively, than prior implementations. Moreover, it does not require any off-chip capacitors. Experimental results from a discrete board-level implementation of the circuit are in good agreement with theoretical predictions.

Quantum dynamical systems are capable of powerful computation but are hard to emulate on digital computers. We show that four novel analog circuit parts can emulate the phase-coherent unitary dynamics of such systems. These four parts are: a Planck capacitance analogous to a neuronal membrane capacitance; a quantum admittance element, together with the Planck capacitance, analogous to a neuronal quadrature oscillator; a quantum transadmittance element analogous to a complex neuronal synapse; and a quantum transadmittance mixer element analogous to a complex neuronal synapse with resonant modulation. These parts may be emulated classically, with paired real-value voltages on paired Planck capacitances corresponding to the real and imaginary portions of a probability amplitude; and appropriate paired real-value currents onto these Planck capacitances corresponding to diagonal (admittance), off-diagonal (transadmittance), or controlled off-diagonal (transadmittance mixer) Hamiltonian energy terms. The superposition of 2n simultaneously phase-coherent and symmetric probability-voltage amplitudes with O(n) of these parts, in a tensor-product architecture enables analog emulation of the quantum Fourier transform (QFT). Implementation of our circuits on an analog integrated circuit in a 0.18 μm process yield experimental results consistent with mathematical theory and computer simulations for emulations of NMR, Josephson junction, and QFT dynamics. Our results suggest that linear oscillatory neuronal networks with pairs of complex subthreshold/nonspiking sine and cosine neurons that are coupled together via complex synapses to other such complex neurons can architect quantum-inspired computation with classical analog circuits. Thus, an analog-circuit mapping between quantum and neural computation, both of which exploit analog computation for powerful operation, can enable future synergies between these fields.

The explosive growth in semiconductor integrated circuits was made possible in large part by design automation software. The design and/or analysis of synthetic and natural circuits in living cells could be made more scalable using the same approach. We present a compiler which converts standard representations of chemical reaction networks and circuits into hardware configurations that can be used to simulate the network on specialized cytomorphic hardware. The compiler also creates circuit-level models of the target configuration, which enhances the versatility of the compiler and enables the validation of its functionality without physical experimentation with the hardware. We show that this compiler can translate networks comprised of mass-action kinetics, classic enzyme kinetics (Michaelis-Menten, Briggs-Haldane, and Botts-Morales formalisms), and genetic repressor kinetics, thereby allowing a large class of models to be transformed into a hardware representation. Rule-based models are particularly well-suited to this approach, as we demonstrate by compiling a MAP kinase model. Development of specialized hardware and software for simulating biological networks has the potential to enable the simulation of larger kinetic models than are currently feasible or allow the parallel simulation of many smaller networks with better performance than current simulation software.

Programmable analog devices have emerged as a powerful computing substrate for performing complex neuromorphic and cytomorphic computations. We present Arco, a new solver that, given a dynamical system specification in the form of a set of differential equations, generates physically realizable configurations for programmable analog devices that are algebraically equivalent to the specified system. On a set of benchmarks from the biological domain, Arco generates configurations with 35 to 534 connections and 28 to 326 components in 1 to 54 minutes.

Although neurons function with locally imprecise analog computational units, they can collectively interact to achieve computations with high complexity, low error rate, or high precision. In this work, we show how many moderately precise integrate-and-fire analog units interact via the mechanism of a spiking `carry' to collectively add numbers to arbitrary precision. For example, in a proof-of-concept implementation that we implemented with chips built in a 0.5 μm CMOS process, we show that four 4-bit precise analog units can collectively interact to implement 16-bit-precise addition. Errors in the analog computation are minimized via novel time-based calibration techniques. Our work may lay a foundation for future collective analog computation that is arbitrarily precise just as current digital computation is today.

We investigate speech-coding strategies for brain-machine-interface (BMI) based speech prostheses. We present an articulatory speech-synthesis system using an experimental integrated-circuit vocal tract that models the human vocal tract. Our articulatory silicon vocal tract makes feasible the transmission of low bit-rate speech-coding parameters over a bandwidth-constrained body sensor network (BSN). To the best of our knowledge, this is the first articulatory speech-prosthesis system reported to date. We also present a speech-prosthesis simulator (SPS) as a means to generate realistic articulatory parameter sequences.

We describe a novel wireless receiver architecture that is a broadband generalization of narrowband heterodyning systems commonly used in radio. It can be constructed with cochlea-like traveling-wave structures. We show how this architecture exploits the efficiency of cochlear spectrum analysis to perform parallel, multi-scale analysis of wideband signals. We discuss analogies between spectrum analysis in our architecture and the process of successive-subranging analog-to-digital conversion. When combined with our prior work on an RF cochlea, such architectures may be useful in cognitive radios for creating “RF foveas” that select the narrowband components present within wideband, but spectrally sparse signals.

This paper describes an ultra-compact analog lithium-ion (Li-ion) battery charger for wirelessly powered implantable medical devices. The charger presented here takes advantage of the tanh output current profile of an operational transconductance amplifier (OTA) to smoothly transition between constant current (CC) and constant voltage (CV) charging regimes without the need for additional area- and power-consuming control circuitry. The proposed design eliminates the need for sense resistors in either the charging path or control loop by utilizing a current comparator to detect end-of-charge. The power management chip was fabricated in an AMI 0.5 μm CMOS process, consuming 0.15 mm2of area. This figure represents an order of magnitude reduction in area from previous designs. An initial proof-of-concept design achieved 75% power efficiency and charging voltage accuracy of 99.8% relative to the target 4.2 V.

We analyze and present an input gain-varying scheme for maximizing dynamic range in a well-known Gm-C bandpass filter by both minimizing noise for small input signals, and by achieving balanced swing levels at all filter nodes for large input signals. A micropower bandpass filter suitable for use in cochlear implants and other power-constrained biomedical applications was implemented and tested in subthreshold CMOS. At a center frequency of 1.4 kHz and quality factor of 4, the filter has 70 dB of dynamic range (57 dB maximum SNR, 2.5% total harmonic distortion (THD)) and consumes 2.55 muW of power.

We exploit the detailed similarities between electronics and chemistry to develop efficient, scalable bipolar or subthreshold log-domain circuits that are dynamically equivalent to networks of chemical reactions. Our circuits can be used for transient and steady-state simulations, parameter estimations and sensitivity analyses of large-scale biochemical networks. They allow the topology, rate constants, inputs, outputs and initial conditions of the reaction network to be programmed. When reactants are present in low concentrations, random fluctuations in reaction rates become significant; we can also model such stochastic effects. We present experimental results from a proof-of-concept chip implemented in 0.18 mum CMOS technology.

This paper presents work on ultra-low-power circuits for brain-machine interfaces with applications for paralysis prosthetics, prosthetics for the blind, and experimental neuroscience systems. The circuits include a micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays; an analog linear decoding and learning architecture for data compression; radio-frequency (RF) impedance modulation for low-power data telemetry; a wireless link for efficient power transfer; mixed-signal system integration for efficiency, robustness, and programmability; and circuits for wireless stimulation of neurons. Experimental results from chips that have recorded from and stimulated neurons in the zebra-finch brain and from RF power-link systems are presented. Circuit simulations that have successfully processed prerecorded data from a monkey brain and from an RF data telemetry system are also presented.

This paper introduces a positive-feedback self-biasing technique for operational amplifiers (op-amps) which enables their power consumption to adapt to their environment: The power consumption of one of our op-amps scales almost linearly with load capacitance, input signal frequency, and output signal swing. Our op-amp is primarily intended for low power switched-capacitor applications. A voltage follower built in the MOSIS/AMI 0.5/spl mu/m process with our op-amp has a measured power consumption that varies between 1.38/spl mu/W and 90/spl mu/W, as the load capacitance varies from 1pF to 100pF.

We describe an approximately-PTAT CMOS current reference circuit that is useful for large analog systems. An innovative capacitively-coupled startup circuit that draws no static power is also presented. Experimental results from 0.5 mum and 0.18 mum implementations are shown. Both references are cascoded and use no resistors. The 0.18 mum version operates down to VDD= 0.5V

We develop a technique for approximating a WKB-type solution to a wave equation as a cascade of unidirectional filters. This allows us to design improved building-block circuits for a bio-inspired RF cochlea. By comparing properties of different cochlear filter stages using experimental results and circuit simulations, we demonstrate that our technique significantly improves the characteristics of the RF cochlea

The voltage droop rate of capacitive analog storage cells is typically limited by the off state leakage of a single MOS switch. Past low-leakage switch designs have assumed that subthreshold conduction and drain-to-bulk diode leakage dominate other effects. However, recent measurements of MOS leakage in a 1.5mum CMOS process have revealed a third important mechanism that can contribute significant leakage. It has been shown that incorporating a novel MOS switch topology into a high-accuracy switched-capacitor storage cell can minimize all of the experimentally observed leakages, achieving 10aA average leakage in a 1.5mum process. This paper presents new experimental data from cells fabricated in a 0.5pm process that exhibit 0.8aA (5e-/sec) average leakage, a 100times reduction over the leading alternative cell in the literature. This implies that with a 1pF storage capacitor and a 3.3V supply, this cell can store a 12-bit accurate voltage for 14.5 minutes and an 8-bit accurate voltage for 3.9 hours. The leakage reduction between the 1.5mum and 0.5mum implementations appears to be reasonable based on simple scaling arguments

Feature computation modules for automatic speech recognition (ASR) systems have long been modeled on the human auditory system. Most current ASR systems model the critical band response and equal loudness characteristics of the auditory system. It has been postulated that more detailed models of the human auditory system can lead to more noise-robust speech recognition. An auditory phenomenon that is of particular relevance to robustness is simultaneous masking, whereby dominant frequencies suppress adjacent weaker frequencies. In this paper, we present a companding-based model that mimics simultaneous masking in the front end of a speech recognizer. In an automotive digits recognition task, the front end improves word error rate by 4.0% (25% relative to Mel cepstra) at -5 dB SNR at the cost of a 1.7% increase at 15 dB SNR.

This work presents a compressing-and-expanding, i.e., companding, strategy for spectral enhancement inspired by the operation of the auditory system. The companding strategy simulates the two-tone suppression phenomena of the auditory system and implements a soft local winner-take-all-like enhancement of the input spectrum. It performs multichannel syllabic compression without degrading spectral contrast. The companding strategy works in an analog fashion without explicit decision making, without the use of the fast Fourier transform, and without any cross-coupling between spectral channels. The strategy is useful in cochlear-implant processors, hearing aids, and speech recognition for enhancing spectral contrast. It is well suited to low-power analog circuit implementations.

We outline a hybrid analog-digital scheme for computing with three important features that enable it to scale to systems of large complexity: First, like digital computation, which uses several one-bit precise logical units to collectively compute a precise answer to a computation, the hybrid scheme uses several moderate-precision analog units to collectively compute a precise answer to a computation. Second, frequent discrete signal restoration of the analog information prevents analog noise and offset from degrading the computation. And, third, a state machine enables complex computations to be created using a sequence of elementary computations. A natural choice for implementing this hybrid scheme is one based on spikes because spike-count codes are digital, while spike-time codes are analog. We illustrate how spikes afford easy ways to implement all three components of scalable hybrid computation. First, as an important example of distributed analog computation, we show how spikes can create a distributed modular representation of an analog number by implementing digital carry interactions between spiking analog neurons. Second, we show how signal restoration may be performed by recursive spike-count quantization of spike-time codes. And, third, we use spikes from an analog dynamical system to trigger state transitions in a digital dynamical system, which reconfigures the analog dynamical system using a binary control vector; such feedback interactions between analog and digital dynamical systems create a hybrid state machine (HSM). The HSM extends and expands the concept of a digital finite-state-machine to the hybrid domain. We present experimental data from a two-neuron HSM on a chip that implements error-correcting analog-to-digital conversion with the concurrent use of spike-time and spike-count codes. We also present experimental data from silicon circuits that implement HSM-based pattern recognition using spike-time synchrony. We outline how HSMs may be used to perform learning, vector quantization, spike pattern recognition and generation, and how they may be reconfigured.

We present a novel technique for performing current-mode analog-to-digital conversion using two integrate-and-fire spiking neurons. The conversion is performed in two steps. The first step is an overranging step that extracts the integer part of the ratio between the input current and a reference current; the second step is a subranging step that extracts the fractional part of this ratio. The conversion is performed by having analog spike-time information in one neuron, the timing neuron, generating digital spike-count information in another neuron, the counting neuron. The roles of the timing neuron and the counting neuron are reversed as we transition between the steps. Operations in the converter are coordinated via a spike-triggered asynchronous finite state machine, obviating the need for a clock to synchronize the internal operations of the converter. We present experimental data from a proof-of-concept VLSI implementation. Because spike number is discrete while interspike intervals are analog, spikes are naturally suited for hybrid computation, i.e., computation that is not purely analog or purely digital but that is a mixture of both forms. Our converter provides an example for the use of such spike-based hybrid computation. The converter is suited for compact, low-power neuromorphic applications.

We review the pros and cons of analog and digital computation. We propose that computation that is most efficient in its use of resources is neither analog computation nor digital computation but, rather, a mixture of the two forms. For maximum efficiency, the information and information-processing resources of the hybrid form must be distributed over many wires, with an optimal signal-to-noise ratio per wire. Our results suggest that it is likely that the brain computes in a hybrid fashion and that an underappreciated and important reason for the efficiency of the human brain, which consumes only 12 W, is the hybrid and distributed nature of its architecture.

This paper discusses some of the fundamental issues in the design of highly parallel, dense, low-power motion sensors in analog VLSI. Since photoreceptor circuits are an integral part of all visual motion sensors, we discuss how the sizing of photosensitive areas can affect the performance of such systems. We review the classic gradient and correlation algorithms and give a survey of analog motion-sensing architectures inspired by them. We calculate how the measurable speed range scales with signal-to-noise ratio (SNR) for a classic Reichardt sensor with a fixed time constant. We show how this speed range may be improved using a nonlinear filter with an adaptive time constant, constructed out of a diode and a capacitor, and present data from a velocity sensor based on such a filter. Finally, we describe how arrays of such velocity sensors call be employed to compute the heading direction of a moving subject and to estimate the time-to-contact between the sensor and a moving object.

An integrated circuit that computes the velocity vector of a visual stimulus in one dimension is presented. The circuit combines optical sensors and associated electronics on a single silicon chip, processed with standard CMOS technology. The velocity is inferred from the time delay of the appearance of an image feature at two fixed locations on the chip. The circuit operates quite robustly for high-contrast stimuli over considerable irradiance and velocity ranges. With lower-contrast stimuli the output signal for a given velocity tends to decrease, while the direction selectivity is still maintained. The individual motion-sensing cells are compact, and they are therefore suited for use in dense 1D or 2D imaging arrays.