A single-band, optically transparent monopole antenna is proposed in this paper. The antenna is intended for wearable technology applications where integration within glass or transparent structures is required such as in smart glasses and wearable displays. The antenna proposed in this paper is designed to have a resonance frequency at 2.4 GHz which enables the Wireless Local Area Network (WLAN) and Bluetooth technologies. The radiating element is deposited on a Pyrex substrate with dimensions of 26.5 mm × 25 mm utilizing a solution of Indium Tin Oxide (ITO). The 3 mm thick Pyrex glass substrate with a dielectric constant of 4.6 was coated with a single layer of ITO via the magnetron sputtering technique. The deposited properties of the coating are as follows: a thickness of 438 nm, sheet resistance of 10.4 Ω/π, and an average optical transmission in the visible light spectrum (λ = 400–750 nm) of 77-87%. Utilizing the photolithography process, the antenna pattern was transferred onto the previously-coated Pyrex by a photosensitive film which then etched out in a solution of HCl, HNO3, and de-ionized (DI) water. The proposed compact and optically transparent design along with the desirable radiation characteristics confirm that it would be a suitable candidate for integration within wearable technology applications that involve glass and/or transparent structures.

High-performance heterogeneous computers that employ field programmable gate arrays (FPGAs) as computational elements are known as high-performance reconfigurable computers (HPRCs). For floating-point applications, these FPGA-based processors must satisfy a variety of heuristics and rules of thumb to achieve a speedup compared with their software counterparts. By way of a simple sparse matrix Jacobi iterative solver, this paper illustrates some of the issues associated with mapping floating-point kernels onto HPRCs. The Jacobi method was chosen based on heuristics developed from earlier research. Furthermore, Jacobi is relatively easy to understand, yet is complex enough to illustrate the mapping issues. This paper is not trying to demonstrate the speedup of a particular application nor is it suggesting that Jacobi is the best way to solve equations. The results demonstrate a nearly threefold wall clock runtime speedup when compared with a software implementation. A formal analysis shows that these results are reasonable. The purpose of this paper is to illuminate the challenging floating-point mapping process while simultaneously showing that such mappings can result in significant speedups. The ideas revealed by research such as this have already been and should continue to be used to facilitate a more automated mapping process.

This paper presents a novel implementation of low power and hardware efficient digital decimation filter. We use multi-stage multi-rate signal processing to design and implement poly-phase half-band FIR filters and a band-pass IIR filter. The band-pass IIR filter is realized by cascading six second order all-pass filters. The decimation filter is designed and simulated using Simulink, DSP blockset and Matlab. The hardware realization of the decimation filter is obtained using FPGA Xilinx technology. The resulting decimation filter has a power reduction of 42% and a hardware saving of 61% compared to conventional decimation filters.

This paper presents a unique design and implementation of a low power decimation filter. The designed decimation filter architecture shows how the 1/3-band IIR filter and a poly-phase half-band FIR filter are used multirate multistage signal processing. The 1/3-band IIR filter is realized using six first order all-pass filters. Each filter stage is simulated using Matlab and, the complete architecture of the decimation filter is captured using Simulink and a DSP blockset. The hardware realization of the decimation filter is obtained using FPGA Xilinx technology. The designed decimation filter reduces the hardware by 59% and the power dissipation by 34% compared to conventional decimation filters.

This paper presents a VLSI implementation of a unique 32-bit antilogarithmic converter, which generates data for some digital-signal-processing (DSP) applications. Novel antilogarithm correcting algorithms are developed and implemented with low-power and hardware-efficient correcting circuits. The VLSI implementations of these algorithms are much smaller than other hardware intensive algorithms found in the literature. The converter is implemented using 0.6 /spl mu/m CMOS technology, and its combinational logic implementation requires 1500/spl lambda//spl times/2800/spl lambda/ of chip area. The 32-bit antilogarithmic converter computes the antilogarithm in a single clock cycle and runs at 100 MHz and consumes 81 mW.

We present a unique 32-bit binary-to-binary logarithm converter including its CMOS VLSI implementation. The converter is implemented using combinational logic only and it calculates a logarithm approximation in a single clock cycle. Unlike other complex logarithm correcting algorithms, three unique algorithms are developed and implemented with low-power and fast circuits that reduce the maximum percent errors that result from binary-to-binary logarithm conversion to 0.9299 percent, 0.4314 percent, and 0.1538 percent. Fast 4, 16, and 32-bit leading-one detector circuits are designed to obtain the leading-one position of an input binary word. A 32-word/spl times/5-bit MOS ROM is used to provide 5-bit integers based on the corresponding leading-one position. Both converter area and speed have been considered in the design approach, resulting in the use of a very efficient 32-bit logarithmic shifter in the 32-bit logarithmic converter. The converter is implemented using 0.6/spl mu/m CMOS technology, and it requires 1,600/spl lambda//spl times/2,800/spl lambda/ of chip area. Simulations of the CMOS design for the 32-bit logarithmic converter, operating at V/sub DD/ equal to 5 volts, run at 55 MHz, and the converter consumes 20 milliwatts.