A new architecture for integrated reliability simulators is presented. The architecture is compatible with analog hardware description language simulation environments. Simulator integration is achieved by incorporating the reliability evaluation routines into the component templates through the use of analog states. An internal simulation control mechanism is substituted for the external control shell found in conventional reliability simulators. The architecture supports iterative and multi-step reliability simulation schemes. A prototype reliability simulator for amorphous silicon circuits is also presented.

A model based on a linearized solution of the Shockley-Read-Hall trapping expressions is presented. It allows these equations to be eliminated from the system matrix. This results in significantly reduced memory requirements and execution times. To illustrate the approach, the switch-on and switch-off transients of a thin-film transistor were simulated. These results are compared with ones obtained from the full two-dimensional transient numerical model. It is shown that the linearized model can simulate a wide variety of device behavior, providing close agreement with the full model at a fraction of the cost.>

A buried-channel (BC) MOSFET model for DC, transient and small-signal circuit simulation, which has been incorporated into SPICE 3B1, is presented. The model includes all of the modes of operation inherent to the BC-MOSFET, including the partial modes of operation. The equivalent circuit for the BC-MOSFET is presented, and the static, transient, and small-signal equations used for SPICE implementation are systematically described. The surface and bulk mobility models used in the static current-voltage characteristic are highlighted. The charge model and the importance of incorporating all of the models of operation are illustrated. A number of examples are given to illustrate the BC-MOSFET SPICE model. It is shown that the SPICE model for the BC-MOSFET is in good agreement with experimental measurements.>

A description is given of CHORD, a semiconductor device simulation development tool created at the University of Waterloo. CHORD is written as several small independent programs which use a centralized database facility and is specifically designed to allow the simple creation, development, and testing of new simulation models and algorithms. Communication between programs is implemented by using a byte-stream process. This allows transfer of information between individual programs running on different machines. CHORD is a general environment in that its models can incorporate any set of user-defined variables of equations. This is illustrated by the development of contact boundary conditions incorporating external circuit elements and circuit-level device models using the modified nodal formulation. Several examples of both steady-state and transient simulations are presented.>

Charge coupled device (CCD) memory technology offers potential economic advantages over semiconductor random-access memory technology. However, the limitations incurred by the serial nature of CCD's have previously restricted their application to computer mainframe memories. The 64 kbyte CCD memory system described in this paper demonstrates the feasibility of CCD memory technology for moderate size memory systems applicable to microcomputer systems. Design objectives included low cost, adequate performance, reliable operation, small size, and low power consumption as well as simple interfacing to standard microprocessors. A simple two-level organization employing a random access memory (RAM) to buffer the serial CCD memory was used to improve the memory system performance and to simplify the interfacing of microcomputers. It is anticipated that the memory system can be easily modified to use 64 kbit and larger CCD memory devices as these become available. Further more, the memory system control logic could be integrated on a single large-scale integration (LSI) chip, thereby facilitating the fabrication of relatively large and economical memory systems with a low component count.