This talk will describe the challenges of high-performance microprocessor designs in 22nm and beyond. The focus of the talk will be on addressing the risks and complexity of this very demanding design domain and what lies beyond the innovation that has been the driving engine of technology so far.

Both the physics and financial challenges of CMOS scaling to 22nm and beyond will be discussed. The effects of the possible slowing of future CMOS technology generations on CMOS chip design and methodology will be hypothesized.

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. The use of smart-body contact to improve the power and delay performance is discussed, as are global design issues.

This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various digital VLSI CMOS circuit families. The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dynamic circuits and wide multiplexers, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.