This work develops an efficient chiplet placer with thermal consideration for 2.5D ICs. Combining the sequence-pair based tree, branch-and-bound method, and advanced placement/pruning techniques, the developed placer can find the solution fast with the optimized total wirelength (TWL) on half-perimeter wirelength (HPWL). Additionally, with the post placement procedure, the placer reduces maximum temperatures with slight increase of wirelength. Experimental results show that the placer can not only find better optimized TWL (reducing 1.035% HPWL) but also speed up at most two orders of magnitude than the prior art. With thermal consideration, the placer can reduce the maximum temperature up to 8.214 °C with an average 5.376% increase of TWL.

Critical systems require extensive simulation effort with functional fault injection on RTL circuits during design stages in order to analyze vulnerability and engineer error-tolerant measures accordingly. Yet for a complex SoC, long simulation cycles are necessary for each injected fault. Therefore it is imperative to prune as many faults as possible to improve simulation efficiency and turn-around time for designers.In this paper, we propose a novel method (ACE-Pro) to reduce the functional fault list. The method extends architecturally correct execution (ACE) analysis by creating a propagation graph, where a node is a fault marked with an ACE bit at a cycle and a directed link between nodes represents the propagation condition to another register at the next cycle. By checking and propagating through the graph the properties of masking (a fault is masked by logic on its propagation path to next registers) and singly-equivalence (a fault is covered by another fault on the next register), we show fault reductions by 98.91% to 99.91% (49.2% to 88.4% from the reduced faults in Equivalent Regions) in our experiments on a RISC-V core.

Shrinking feature sizes and cell capacitances, lower operation voltages, and higher operation speeds intensify the influences of radiation-induced soft-errors. To guarantee the functional safety of electronic systems, designers need effective techniques to evaluate designs under errors. Fault injection is one of the standard assessment tools for system dependability. However, because traditional RTL fault simulation has become too slow for modern complex systems, we need abstraction models for early-stage system reliability analysis and design. In this paper, we present an accurate reliability assessment SystemC fault simulator. It features a dynamic mechanism for injecting faults and analyzing the produced errors to evaluate possible fault detection and tolerance designs. Our experimental results show that our simulator can achieve 470x speedup on accurate architecture register fault simulation, validated with the RTL model.

Traditionally, the EPQ model is the most widely used method to solve the production problem. This model is based on ideal production process conditions, with the final products within the specifications and without any defects and the result is significantly different from the actual production system. In reality, a manufacturer encounters a number of uncertainties, such as quality variance, equipment unreliability, and defects and shortage incurred from imperfect production planning, implementation, and processing. Over the past few decades, majority of related EQP studies, based on a single factor or multiple factors, were too complicated to use. This publication is intended to investigate the possible alternatives on imperfect production and quality variance in the production environment by using Fuzzy AHP to evaluate the most critical alternatives. The EPQ model based on these critical factors will determine the alternatives for the optimum Economic Production Quantity, meanwhile an adaptive (s, S) production system can be determined accordingly.