EDBT 2026 Demo / reviewers in the wild / expert
Thomas Lundqvist
dblp:46/4033
· DBLP profile ↗
4ranked-venue papers
2as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorComputer networks · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Embedded and real-time systems · 38% Parallel and multicore computing · 38% Memory systems · 23% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › task scheduling › dynamic scheduling
dynamically-scheduled processor |
0.0 | 1 | 1999 | Timing Anomalies in Dynamically Scheduled Microprocessors · RTSS 1999 |
Embedded and real-time systems
worst-case execution time analysis |
0.0 | 1 | 1999 | Timing Anomalies in Dynamically Scheduled Microprocessors · RTSS 1999 |
Memory systems
cache |
0.0 | 1 | 1999 | Timing Anomalies in Dynamically Scheduled Microprocessors · RTSS 1999 |
Memory systems › cache
cache miss |
0.0 | 1 | 1999 | Timing Anomalies in Dynamically Scheduled Microprocessors · RTSS 1999 |
Methods — techniques the papers use, named apart from their topics
code modification · 0.0WCET estimation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | Flipping the Data Center Network: Increasing East-West Capacity Using Existing HardwareabstractIn today's datacenters, there is an increasing demand for more network traffic capacity. The majority of the increase in traffic is internal to the datacenter, i.e., it flows between different servers within the datacenter. This category of traffic is often referred to as east-west traffic and traditional hierarchical architectures are not well equipped to handle this type of traffic. Instead, they are better suited for the north-southbound traffic between hosts and the Internet. One suggested solution for this capacity problem is to adopt a folded CLOS topology, also known as spine-leaf, which often relies on software defined network (SDN) controllers to manage traffic. This paper shows that it is possible to implement a spine-leaf network using commodity-ofthe-shelf switches and thus improve the east-west traffic capacity. This can be obtained using low complexity configuration and edgerouting for load balancing, eliminating the need for a centralized SDN controller. H. Robert H. Andersson, Andreas de Blanche, Thomas Lundqvist |
LCN | 3 |
| 2015 | Addressing characterization methods for memory contention aware co-scheduling
Andreas de Blanche, Thomas Lundqvist |
J. Supercomput. | 2 |
| 1999 | Timing Anomalies in Dynamically Scheduled MicroprocessorsabstractPrevious timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wrong in dynamically scheduled processors. A cache miss, for example, can in some cases result in a shorter execution time than a cache hit. Many examples of such timing anomalies are provided. We first provide necessary conditions when timing anomalies can show up and identify what architectural features that may cause such anomalies. We also show that analyzing the effect of these anomalies with known techniques results in prohibitive computational complexities. Instead, we propose some simple code modification techniques to make it impossible for any anomalies to occur. These modifications make it possible to estimate WCET by known techniques. Our evaluation shows that the pessimism imposed by these techniques is fairly limited; it is less than 27% for the programs in our benchmark suite. Thomas Lundqvist, Per Stenström |
RTSS | 1 |
| 1999 | An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution
Thomas Lundqvist, Per Stenström |
Real Time Syst. | 1 |