The recent development of multi-agent simulations brings about a need for population synthesis. It is a task of reconstructing the entire population from a sampling survey of limited size (1% or so), supplying the initial conditions from which simulations begin. This paper presents a new kernel density estimator for this task. Our method is an analogue of the classical Breiman-Meisel-Purcell estimator, but employs novel techniques that harness the huge degree of freedom which is required to model high-dimensional nonlinearly correlated datasets: the crossover kernel, the k-nearest neighbor restriction of the kernel construction set and the bagging of kernels. The performance as a statistical estimator is examined through real and synthetic datasets. We provide an "optimization-free" parameter selection rule for our method, a theory of how our method works and a computational cost analysis. To demonstrate the usefulness as a population synthesizer, our method is applied to a household synthesis task for an urban micro-simulator.

As the variations of shrunk processes increasing at rapid rate, the performances of analog/mixed-signal chips remarkably fluctuate. It is necessary to take the yield as a design objective in design optimization. This paper presents a novel method to generate yield-embedded Pareto-front to simultaneously optimize both the yield and performances. Unlike the traditional approaches which generate the yield-aware Pareto-front to optimize performances for the fixed yield, this work embeds the yield as an objective of the optimization and evolutionarily optimizes both yield and performances by the so-called yield-embedded NSGA. The experiments demonstrate the gradual evolutions and global searching for the better performances and higher yields under PVT variations. The generation accelerated by parallel computations gains 4.8x speedup with 80% efficiency.

This paper presents a new method using multi-objective optimization algorithm to automatically find the best solution from a topology library of analog circuits. Firstly this method abstracts the Pareto-front of each topology in the library by SPICE simulation. Then, the Pareto-front of the topology library is abstracted from the Pareto-fronts of topologies in the library followed by the theorem we proved. The best solution which is defined as the nearest point to specification on the Pareto-front of the topology library is then calculated by the equations derived from collinearity theorem. After the local searching using Nelder-Mead method maps the calculated best solution back to design variable space, the non-dominated best solution is obtained.

Statistical timing analysis (SSTA) is a method that calculates circuit delay statistically with process parameter variations, die-to-die (D2D) and within-die (WID) variations. In this paper, we model that WID parameter variations are independent for each cell and line in a chip and D2D variations are governed by one variation on a chip. We propose a new method of computing a full chip delay distribution considering both D2D and WID parameter variations. Experimental results show that the proposed method is more accurate than previous methods on actual chip designs.

This paper describes the delay calculation method and the accuracy analysis of its interpolation for CMOS ASIC libraries which contain cell-based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification, and logic synthesis. The delay calculation method addressed in this paper is specified as IEC CDV 61523-2 standard which consists of the estimation of wire capacitance, and the delay calculation method based on a table look-up. Although the input to the delay calculator is net list and library parameters, the delay parameter part of the library has not been standardized because of its strong dependency on the delay calculation method. We, IEC/TC93/WG2/ALR group, specified it based on the EIAJ work. In IEC CDV 61523-2, we specified in detail a table look up calculation formula for CMOS ASIC library using a linear interpolation in the triangular area which is more accurate than the bilinear interpolation. In this paper, we overview the specification and provide the mathematical background for the interpolation.