Demo Data from EDBT 2026 / reviewers in the wild / expert
Olivier Peyran
dblp:46/4339
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › design optimization
area optimization |
0.0 | 1 | 2004 | Area optimization of delay-optimized structures using intrinsic constraint graphs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004 |
Electronic design automation
physical design |
0.0 | 1 | 2004 | Area optimization of delay-optimized structures using intrinsic constraint graphs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004 |
Electronic design automation › physical design
placement |
0.0 | 1 | 2004 | Area optimization of delay-optimized structures using intrinsic constraint graphs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1998 | Retiming DAGs [direct acyclic graph] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998 |
Electronic design automation › logic synthesis › sequential circuit optimization
retiming |
0.0 | 1 | 1998 | Retiming DAGs [direct acyclic graph] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998 |
Electronic design automation
timing analysis |
0.0 | 1 | 1998 | Retiming DAGs [direct acyclic graph] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998 |
Methods — techniques the papers use, named apart from their topics
structure extraction · 0.0intrinsic constraint graphs · 0.0block-sizing algorithm · 0.0low-complexity algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | Area optimization of delay-optimized structures using intrinsic constraint graphsabstractIn this paper, we present a new methodology for structure optimization of block-based design. Instead of merging area and delay criteria, we segregate them into two independent steps. Solutions optimized for delay in the first step are optimized for area with a block-sizing algorithm in the second step. The fully optimized solutions eventually return to the first optimization step, if the user constraints are not met, using a structure-extraction module. A condition to this approach is that the area optimization phase does not alter the quality reached during delay optimization. We propose a framework for area optimization of delay-optimized structures based on structure similarities. We present a new model to represent block placements that share the same qualities for global routing. Using this model, we formally define the relation of similarity and exhibit several properties and theorems to validate our approach. The modules composing the area optimization phase are presented and experimental results confirm the validity of our methodology. Olivier Peyran, Wenjun Zhuang |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2002 | Transforming Arbitrary Structures into Topologically Equivalent Slicing StructuresabstractFloorplanning is an important step of IC design. Traditionally, floorplan representation has been segregated between slicing and non-slicing structures. We present a heuristic that translates any arbitrary structure into a slicing one, topologically equivalent to the initial one after a 1-D compaction. Olivier Peyran, Wenjun Zhuang |
DATE | 1 |
| 1998 | Retiming DAGs [direct acyclic graph]abstractThis paper is devoted to a low-complexity algorithm for retiming circuits without cycles, i.e., those whose network graph is a direct acyclic graph (DAG). On one hand, DAGs have a great practical importance, as shown by the on-line arithmetic circuits used as a target application in this paper. On the other hand, retiming is a costly design optimization technique, in particular when applied to large circuits. Hence the need to design a specialized retiming algorithm to handle DAGs more efficiently than general-purpose retiming algorithms. Our algorithm dramatically improves on current solutions in the literature. We gain an order of magnitude in the worst case complexity, and we show convincing experimental results at the end of this paper. Pierre-Yves Calland, Anne Mignotte, Olivier Peyran, Yves Robert, Frédéric Vivien |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |