EDBT 2026 Demo / reviewers in the wild / expert
C. O. Newton
dblp:46/5265
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1983
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
gate array design |
0.0 | 1 | 1983 | The UK5000 - successful collaborative development of an integrated design system for a 5000 gate CMOS array with built-in test · DAC 1983 |
Electronic design automation › physical design › routing
global routing |
0.0 | 1 | 1983 | Optimisation of global routing for the UK5000 gate array by iteration · DAC 1983 |
Electronic design automation
physical design |
0.0 | 1 | 1983 | Optimisation of global routing for the UK5000 gate array by iteration · DAC 1983 |
Electronic design automation › hardware verification and test › design for testability
built-in self-test |
0.0 | 1 | 1983 | The UK5000 - successful collaborative development of an integrated design system for a 5000 gate CMOS array with built-in test · DAC 1983 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1983 | The UK5000 - successful collaborative development of an integrated design system for a 5000 gate CMOS array with built-in test · DAC 1983 |
Methods — techniques the papers use, named apart from their topics
iterative optimization · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1983 | The UK5000 - successful collaborative development of an integrated design system for a 5000 gate CMOS array with built-in test
J. R. Grierson, B. Cosgrove, Daniel Richert, R. E. Halliwell, Harold Kirk, John C. Knight, John A. McLean, J. M. McGrail, C. O. Newton |
DAC | 9 |
| 1983 | Optimisation of global routing for the UK5000 gate array by iteration
C. O. Newton, Patricia A. Young |
DAC | 1 |