This special panel session brings together several leading technologists to discuss the challenges and solutions in constructing SoC designs that achieve their performance goals within a very tight power budget. These challenges are addressed from the often conflicting perspectives of semiconductor design teams and commercial solutions providers of EDA construction tools, EDA analysis tools and semiconductor IP (SIP).

This tutorial presents an overview of timing verification techniques which are used in the synthesis of IC layout.Issues which are covered include: delay estimation, transistor sizing, timing-driven placement and routing, circuit extraction, timing analysis and timing simulation.The role of each of these analysis techniques in the design flow is presented and numerous examples of associated CAD tools are described.

The authors have reduced the uncertainty inherent in timing analysis due to lack of proper signal interaction modeling and delay evaluation inaccuracy. They have refined the false path elimination algorithms which place upper or lower bounds on the maximum settling time of a network by generalizing the application of logical constraints to time intervals. The proposed method allows simultaneous changes on inputs for path excitation, identifies glitches which cannot propagate, and improves the handling of reconvergent paths. The algorithm presented is based on an evolution of the LSP (longest stability sensitizable path) algorithm and derives multiple test vectors to excite the path as part of the search and elimination process. The timing analyzer is tightly linked to an electrical simulator which is used for verification of candidate paths.>

A new approach to the false path problem in timing verifiers is presented. This approach is based on the modeling of both the logic and timing behavior of a circuit. Using the logic propagation conditions associated with each delay, efficient algorithms have been developed to find statically sensitizable paths. These algorithms simultaneously perform a longest path search and a partial verification of the sensitization of the paths. The resulting paths undergo a final and complete sensitization. The algorithms find the longest statically sensitizable path, whose length is a lower bound to the critical path length, and its associated sensitizing input vector. The algorithms can be easily modified to provide an ordered list of all the statically sensitizable paths above a given threshold. An initial analysis of the circuit by the PERT algorithm guides the critical path search and allows pruning of subgraphs that cannot lead to the solution. Results show that these techniques succeed in curbing the combinatorial explosion associated with the longest statically sensitizable path search.>

A new multi-level macromodeling technique for timing simulation has been developed. This technique is based upon the modeling of the behavior of subcircuits under single input changes. The possible interactions between multiple input changes determine the range of validity of the models. A formal method for developing the model validity conditions is presented. This work establishes a bridge between timing analysis by using single input change models, and timing simulation which correctly models signal interactions. The availability of a formal criterion for the validity of the models allows the dynamic identification of the parts of the circuit that require more accurate models. As a result, the cost advantage of high level models can be fully exploited while still allowing critical interactions to be simulated with high accuracy.

Using a formal modeling of the signal interactions, a statistical timing simulator capable of detecting delay faults and computing delay defect distributions has been built. This tool produces the delay fault statistics which must be used by delay fault ATPG (automatic test pattern generation) tools if they are to model process-induced delay failures realistically. The most obvious application for this tool is the computation of the probability of failure due to parametric delay faults. For this application, a Monte Carlo experiment was performed with a single nominal simulation followed by many timing reevaluations.>

This paper describes a new approach for timing analysis in general and, more specifically, for statistical timing analysis. A methodology based upon the utilization of the design hierarchy for circuit partitioning and building of the simulation hierarchy was developed. The logic and timing behaviors of the blocks resulting from the partitioning are dissociated and modeled separately. The logic model is represented by an equivalent finite state machine while an automated characterization process extracts the timing data from multiple circuit simulations in order to build a parametric timing model. These models provide the basis of an event-driven hierarchical timing simulator which can be used as a stand-alone tool but also as a front end for statistical timing analyses. Both the nominal and the statistical simulators have been implemented within STAT! (Statistical Timing Analysis Tool), and the results obtained for a few test cases are presented here.