Demo Data from EDBT 2026 / reviewers in the wild / expert
Chenggang Xu
dblp:46/5561
· DBLP profile ↗
6ranked-venue papers
4as first author
1since 2021 · last 2025
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 4 first-authorArtificial intelligence and machine learning · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Electronic design automation · 83% Integrated circuit design · 17% | |
| Theoretical computer science
2 papers |
Mathematical optimization · 100% | |
| Computer graphics and multimedia
1 paper |
Image and video coding · 100% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
parasitic extraction |
0.2 | 3 | 2008 | Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 A green function-based parasitic extraction method for inhomogeneous substrate layers · DAC 2005 |
Electronic design automation › circuit modeling
substrate coupling modeling |
0.1 | 1 | 2005 | On the numerical stability of Green's function for substrate coupling in integrated circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005 |
Mathematical optimization › numerical analysis
boundary element method |
0.0 | 1 | 2008 | Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Image and video coding › transform coding
discrete cosine transform |
0.0 | 1 | 2006 | An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Electronic design automation
design for manufacturability |
0.0 | 1 | 2005 | A green function-based parasitic extraction method for inhomogeneous substrate layers · DAC 2005 |
Mathematical optimization › numerical analysis
numerical stability |
0.0 | 1 | 2005 | On the numerical stability of Green's function for substrate coupling in integrated circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005 |
Methods — techniques the papers use, named apart from their topics
green's function · 0.3volume meshing · 0.2discrete transforms · 0.2boundary-element meshing · 0.2interpolation · 0.1error control · 0.1discrete cosine transform · 0.1numerical analysis · 0.1green function method · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Interval Secure Event-Triggered Mechanism for Load Frequency Control Active Defense Against DoS AttackabstractThis study proposes an active defense strategy against denial-of-service (DoS) attacks to address the secure event-triggered control of multiarea load frequency control (LFC) systems. A novel interval secure event-triggered mechanism (ISETM) is introduced, integrating event-triggered control with cybersecurity mechanisms under the software defined network (SDN) framework. ISETM generates not only a triggering instant but also a secure triggering interval (STI) simultaneously. The STI sent to the SDN control plane is an estimation time interval generated by the Taylor expansion and model-based prediction method. During this interval, the SDN control plane programs OpenFlow switches to filter attack traffics, ensuring delayed but secure triggering transmission. Under ISETM conditions represented by two systems of inequalities, a multiarea LFC system is modeled as a delay system incorporating a triggering error based on the Taylor expansion. To achieve performance of the established LFC system, a criterion is derived using the Lyapunov-Krasovskii functional method. A codesign approach is provided to solve the proposed ISETM control (ISETC) gains through linear matrix inequality (LMI) techniques. Finally, simulations validate the effectiveness and advantages of our proposed method. Zihao Cheng 0002, Songlin Hu 0002, Dong Yue 0001, Xuhui Bu, Xiaolong Ruan, Chenggang Xu |
IEEE Trans. Cybern. | 6 |
| 2008 | Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based MethodabstractA new green function-based method for extracting parasitics in inhomogeneous substrates is presented. This approach overcomes the limitation of prior green function-based methods and allows extraction of substrate parasitics in the presence of sinkers, trenches, and wells. A careful use of volume and boundary-element meshing, as well as discrete transforms, yields a technique that is computationally efficient. The accuracy of the method is comparable to that of 3-D semiconductor device simulators with significantly smaller computational costs. Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2006 | An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICsabstractThis paper presents an error control method for application of the discrete cosine transform (DCT) to extraction of substrate parasitics in integrated circuits. In addition to the truncation error with approximating an infinite series with a finite number of terms, there are also errors in approximating the truncated series by the DCT. It is shown that this error is important for accurate parasitic extraction and isolation calculation and can be controlled by applying an interpolation method. The interpolation method also makes it possible to use a smaller DCT size without loss of accuracy. Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2005 | A green function-based parasitic extraction method for inhomogeneous substrate layersabstractThis paper presents a new Green function-based approach for substrate parasitic extraction in substrates with inhomogeneous layers. This new formulation allows analysis of noise coupling with sinkers, trenches and wells, - a limitation in prior Green function-based extractors. Numerical examples for sinkers and trenches are provided and compared with the results from threedimensional semiconductor device simulations. It is shown that the proposed method is accurate and computationally efficient. Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram |
DAC | 1 |
| 2005 | On the numerical stability of Green's function for substrate coupling in integrated circuitsabstractThis paper presents an analysis of the numerical stability for the formulation of the Green's function method of Niknejad et al. (1998) for modeling and analysis of substrate coupling in integrated circuits. It is shown that the formulation has numerical overflow problems. A new stable formulation is presented. Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2005 | Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element SolverabstractThis paper presents an automated methodology for calibrating the doping profile and accurately predicting substrate parasitics with boundary element solvers. The technique requires fabrication of only a few test structures and results in an accurate three-layered approximation of a heavily doped epitaxial silicon substrate. Using this approximation, the extracted substrate resistances are accurate to within 10% of measurements. The calibrated parasitic extractor results in good agreement between simulations and measurements for substrate noise coupling in fabricated test circuits. Ajit Sharma, Patrick Birrer, Sasi Kumar Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram |
IEEE Trans. Very Large Scale Integr. Syst. | 4 |