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Chris Wolff

dblp:46/5885 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2002
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
design flow
0.012002
Automated timing model generation · DAC 2002
Electronic design automation › design methodology
hierarchical design
0.012002
Automated timing model generation · DAC 2002
Electronic design automation › system-level design
IP reuse
0.012002
Automated timing model generation · DAC 2002
Electronic design automation
timing analysis
0.012002
Automated timing model generation · DAC 2002
Electronic design automation
timing model generation
0.012002
Automated timing model generation · DAC 2002

Methods — techniques the papers use, named apart from their topics

static timing analysis · 0.0
YearPublicationVenuePosition
2002 Automated timing model generation
abstract
The automated generation of timing models from gate-level netlists facilitates IP reuse and dramatically improves chip-level STA runtime in a hierarchical design flow. In this paper we discuss two different approaches to model generation, the design flows they lend themselves to and results from the application of these model generation solutions to large customer designs.
Ajay J. Daga, Loa Mize, Subramanyam Sripada, Chris Wolff, Qiuyang Wu
DAC4