As sensor networks operate over long periods of deployment in difficult to reach places, their requirements may change or new code may need to be uploaded to them. The current state-of-the-art protocols (Deluge and MNP) for network reprogramming perform the code dissemination in a multihop manner using a three-way handshake where metadata is exchanged prior to code exchange to suppress redundant transmissions. The code image is also pipelined through the network at the granularity of pages. In this article we propose a protocol called Freshet for optimizing the energy for code upload and speeding up the dissemination if multiple sources of code are available. The energy optimization is achieved by equipping each node with limited nonlocal topology information which it uses to determine the time when it can go to sleep since code is not being distributed in its vicinity. The protocol to handle multiple sources provides a loose coupling of nodes to a source and disseminates code in waves each originating at a source with a mechanism to handle collisions when the waves meet. The protocol's performance with respect to reliability, delay, and energy consumed is demonstrated through analysis, simulation, and implementation on the Berkeley mote platform.

Since sensor data gathering is the primary functionality of sensor networks, it is important to provide a fault tolerant method for reasoning about sensed events in the face of arbitrary failures of nodes sending in the event reports. In this paper, we propose a protocol called TIBFIT to diagnose and mask arbitrary node failures in an event-driven wireless sensor network. In our system model, sensor nodes are organized into clusters with rotating cluster heads. The nodes, including the cluster head, can fail in an arbitrary manner generating missed event reports, false reports, or wrong location reports. Correct nodes are also allowed to make occasional natural errors. Each node is assigned a trust index to indicate its track record in reporting past events correctly. The cluster head analyzes the event reports using the trust index and makes event decisions. TIBFIT is analyzed and simulated using the network simulator ns-2 and its coverage evaluated with a varying number and varying intelligence of the malicious nodes. We show that once TIBFIT gathers enough system state, accurate event detection is possible even if more than 50% of the network nodes are compromised.

With the development of location aware sensor applications, location determination has become an increasingly important middleware technology. Numerous current technologies for location determination of sensor nodes use the received signal strength from sensor nodes using omnidirectional antennas. However, an increasing number of sensor systems are now deploying directional antennas due to their advantages like energy conservation and better bandwidth utilization. In this paper, we present techniques for location determination in a sensor network with directional antennas under different kinds of deployment of the nodes. We show how the location estimation problem can be solved by measuring the received signal strength from just one or two anchors in a 2D plane with directional antennas. We implement our technique using Berkeley MICA2 sensor motes and show that it is up to three times more accurate than triangulation using omnidirectional antennas. We also perform Matlab simulations that show the accuracy of location determination with increasing node density

Multilevel test access mechanism (TAM) optimization is necessary for modular testing of hierarchical systems-on-chip (SOCs) that contain older-generation SOCs as embedded megacores. We consider the case where these older-generation SOCs are used as hard cores in new SOC designs, and they are delivered to the system integrator as optimized and technology-mapped layouts. We present three hierarchical test planning and TAM optimization flows that exploit recent advances in TAM design for flattened SOC hierarchies. These techniques are based on the reuse of existing TAM architectures within megacores and the optimization of the top-level TAM under the constraints imposed by "TAM-ed" megacores that are delivered either with or without a wrapper. We present a new megacore wrapper-design technique for the latter case. Unlike prior methods that assume flat test hierarchies, the proposed methods are directly applicable to real-world design-transfer models involving hard megacores between the core vendor and the system integrator for hierarchical SOCs. Experimental results are presented for four ITC'02 SOC test benchmarks that contain megacores.

Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically run at lower frequencies (10-50 MHz). The use of high-speed ATE channels to drive slower scan chains leads to an underutilization of resources, thereby resulting in an increase in testing time. We present a new technique to reduce the testing time and test cost by matching high speed ATE channels to slower scan chains using the concept of virtual test access mechanisms (TAMs). We also present a new TAM optimization framework based on Lagrange multipliers. Experimental results are presented for three industrial circuits from the ITC'02 SOC test benchmarks.

Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimization flows that exploit recent advances in TAM design for flattened SOC hierarchies. Unlike prior methods that assume flat test hierarchies, the proposed methods are directly applicable to real-world design transfer models between the core vendor and the SOC integrator. Experimental results are presented for four ITC'02 SOC test benchmarks.