Modern and future AI-based automotive applications, such as autonomous driving, require the efficient real-time processing of huge amounts of data from different sensors, like camera, radar, and LiDAR. In the ZuSE-KI-AVF project, multiple university, and industry partners collaborate to develop a novel massive parallel processor architecture, based on a cus-tomized RISC-V host processor, and an efficient high-performance vertical vector coprocessor. In addition, a software development framework is also provided to efficiently program AI-based sensor processing applications. The proposed processor system was verified and evaluated on a state-of-the-art UltraScale+ FPGA board, reaching a processing performance of up to 126.9 FPS, while executing the YOLO-LITE CNN on 224x224 input images. Further optimizations of the FPGA design and the realization of the processor system on a 22nm FDSOI CMOS technology are planned.

Embedded systems’ hardware and software stacks are becoming more complex requiring more development time, time to market, and cost, which contributes to delayed delivery of these silicon devices. A virtual prototype (VP) provides an embedded systems architecture simulator for application development and testing purposes. In this paper, we developed and present the first virtual prototype of the Xtensa LX7 microprocessor that evaluates the performance of its emulated hardware performance counters (HPCs) with those collected from an actual Xtensa LX7 hardware. Seven machine learning models were developed and trained to find the relationships between the two different datasets for the sample application of classifiying return-oriented programming (ROP) attacks. Our experiments show that the obtained micro-architectural characteristics on the VP are on average about 70% similar and thus permit early simulation capabilities for developers and testers.

The requirements of ISO26262 for the development of safety-critical Integrated Circuits (IC) demand substantial efforts on fault analysis for safety metrics evaluation. Failing to achieve the required conditions entails modifications to the circuit, additional iterations through critical design phases, and consequently extra costs and delays. For that reason, providing accurate methods to estimate safety metrics is of great importance. This paper proposes a methodology that can efficiently and precisely estimate the safety metrics of Automotive designs. The technique is based on the characterization of a netlist to determine how hardware components contribute to fault propagation. Also, by examining the test stimuli applied during simulation, we can rank Workloads/Testbenches according to their fault detection coverage. The approach was verified running fault injection campaigns on distinct gate-level hardware designs, including an Automotive CPU. Our results show that the fault detection coverage can be estimated with an average error rate of 3% at up to 20X faster execution times when compared to the traditional campaigns. Hence the methodology provides an efficient and cost-effective mechanism to support engineers in a confident design space exploration.

The current demands for developing safe automotive applications require extensive analysis and evaluation of potential random hardware faults. In general, part of this analysis is manually performed by experts, resulting in an expensive, time-consuming, and error-prone process. This paper proposes an automated approach to classify faults overlooked by traditional methods. Our methodology deploys code coverage and formal to identify nodes that do not disrupt safety-critical functionalities, enabling the classification of additional faults. The approach is validated based on an Automotive CPU, according to ISO 26262 guidelines. The results show an improvement in Diagnostic Coverage of 1.15%, increasing the Single Point Fault Metric (SPFM) to 97.3%, enabling ASIL C compliance without any hardware redundancy.

The recent trends for nanoelectronic computing systems include machine-to-machine communication in the era of Internet-of-Things (IoT) and autonomous systems, complex safety-critical applications, extreme miniaturization of implementation technologies and intensive interaction with the physical world. These set tough requirements on mutually dependent extra-functional design aspects. The H2020 MSCAITN project RESCUE is focused on key challenges for reliability, security and quality, as well as related electronic design automation tools and methodologies. The objectives include both research advancements and cross-sectoral training of a new generation of interdisciplinary researchers. Notable interdisciplinary collaborative research results for the first halfperiod include novel approaches for test generation, soft-error and transient faults vulnerability analysis, cross-layer fault-tolerance and error-resilience, functional safety validation, reliability assessment and run-time management, HW security enhancement and initial implementation of these into holistic EDA tools.

The development of Integrated Circuits for the Automotive sector imposes on major challenges. ISO26262 compliance, as part of this process, entails complex analysis for the evaluation of potential random hardware faults. This paper proposes a systematic approach to identify faults that do not disrupt safety-critical functionalities and consequently can be considered Safe. By deploying code coverage and Formal verification techniques, our methodology enables the classification of faults that are unclassified by other technologies, improving ISO26262 compliance. Our results, in combination with Fault Simulation, achieved a Diagnostic Coverage of 93% in a CAN Controller. These figures allow an initial assessment for an ASIL B configuration of the IP.

The advanced complex electronic systems increasingly demand safer and more secure hardware parts. Correspondingly, fault injection became a major verification milestone for both safety- and security-critical applications. However, fault injection campaigns for gate-level designs suffer from huge execution times. Therefore, designers need to apply early design evaluation techniques to reduce the execution time of fault injection campaigns. In this work, we propose a method to represent gate-level Single-Event Transient (SET) faults by multiple Single-Event Upset (SEU) faults at the Register-Transfer Level. Introduced approach is to identify true and false logic paths for each SET in the flip-flops' fan-in logic cones to obtain more accurate sets of flip-flops for multiple SEUs injections at RTL. Experimental results demonstrate the feasibility of the proposed method to successfully reduce the fault space and also its advantage with respect to state of the art. It was shown that the approach is able to reduce the fault space, and therefore the fault-injection effort, by up to tens to hundreds of times.

The current demands for autonomous driving generated momentum for an increase in research in the different technologies required for these applications. Nonetheless, the limited access to representative designs and industrial methodologies poses a challenge to the research community. Considering this scenario, there is a high demand for an open-source solution that could support development of research targeting automotive applications. This paper presents the current status of AutoSoC, an automotive SoC benchmark suite that includes hardware and software elements and is entirely open-source. The objective is to provide researchers with an industrial-grade automotive SoC that includes all essential components, is fully customizable, and enables analysis of functional safety solutions and automotive SoC configurations. This paper describes the available configurations of the benchmark including an initial assessment for ASIL B to D configurations.

The development of Integrated Circuits for the Automotive sector imposes on complex challenges. ISO26262 Functional Safety requirements entail extensive Fault Injection campaigns and complex analysis for the evaluation of deployed Software Tools. This paper proposes a methodology to improve Fault Analysis Tools Confidence Level (TCL) by detecting errors in the classification of faults. By combining the strengths of Automatic Test Pattern Generators (ATPG), Formal Methods and Fault Injection Simulators we are able to automatically generate a Test Environment that enables the validation of the tools and provides supplementary information about the design behavior. Our results showed fault detection rates above 99% including information to improve ISO26262 metrics calculation

This work proposes a fault injection methodology where Hardware Description Language (HDL) code slicing is exploited to prune fault injection locations, thus enabling more efficient campaigns for safety mechanisms evaluation. In particular, the dynamic HDL slicing technique provides for a highly collapsed critical fault list and allows avoiding injections at redundant locations or time-steps. Experimental results show that the proposed methodology integrated into commercial tool flow doubles the simulation speed when comparing to the state-of-the-art industrial-grade EDA tool flows.

Tolerance to random hardware failures, required by ISO26262, entails accurate design behavior analysis, complex Verification Environments and expensive Fault Injection campaigns. This paper proposes a methodology combining the strengths of Automatic Test Pattern Generators (ATPG), Formal Methods and Fault Injection Simulation to decrease the efforts of Functional Safety Verification. Our methodology results in a fast-deployed Fault Injection environment achieving Fault detection rates higher than 99% on the tested designs. In addition, ISO26262 Tool Confidence level is improved by a fault analysis report that allows verification of malfunctions in the outputs of the tools.

Today's virtual prototypes model complex manycore platforms. In application domains such as network processing, they may comprise hundreds of processors, which makes simulation speed the key issue due to the single-threaded execution semantics of SystemC. We propose CoMix, the Concurrent Model Interface, for the distributed simulation of large-scale SystemC models. CoMix provides robust communication between peers, enables their loose synchronization, and manages the overall life cycle. It is an overlay technology neither requiring modified simulators nor depending on a hosts' communication infrastructure. The CoMix library is small (2k Lines of Code) and easily deployable. We quantify its overhead on synthetic benchmarks and observe reasonable speedups for synthetic benchmarks and a large real-world example, e.g., 3.3X and 4X for a 4-peer simulation.

For ad-hoc home networks without central coordinator, IEEE 802.11 systems merely support service differentiation. In many usage scenarios of a typical home network with applications requiring a strict quality of service (QoS), this MAC functionality is not sufficient. In order to counteract this problem, we developed in previous works a modified MAC scheme based on the IEEE 802.11 enhanced distributed channel access (EDCA) function. This paper describes enhancements of the modified MAC scheme enforcing prioritized medium access for strict QoS applications. For the first time, the established concept is realized in a distributed way with in-band signaling. Our enhanced MAC is embedded into a comprehensive IEEE 802.11n reference application to demonstrate its effectiveness in combination with the latest amendments like frame aggregation. The reference application is modeled in SystemClick, a framework for describing and evaluating packet processing applications on resource constraint network nodes. This enables functional validation and provides a path to future, cost-efficient implementations on programmable devices. On this basis, the paper presents simulation results substantiating the significant improvement of QoS parameters like delay and throughput. Besides enforcing strict priorities, collisions can be reduced to zero and the average waiting time can be decreased by up to 33 % for typical usage scenarios.

Wireless network (WLAN) platforms today are based on complex and inflexible hardware solutions to meet performance and deadline constraints for media access control (MAC). Contrary to that, physical layer solutions, such as software defined radio, become more and more flexible and support several competing standards. A flexible MAC counterpart is needed for system solutions that can keep up with the rising variety of WLAN protocols. We revisit the case for programmable MAC implementations looking at recent WLAN standards and show the feasibility of a software-based MAC. Our exploration uses IEEE 802.11a-e as design driver, which makes great demands on Quality-of-Service, security, and throughput. We apply our SystemC framework for efficiently assessing the quality of design points and reveal trade-offs between memory requirements, core performance, application-specific optimizations, and responsiveness of MAC implementations. In the end, two embedded cores at moderate speed (< 200 MHz) with lightweight support for message passing using small buffers are sufficient for sustaining worst-case scenarios in software.

Designing efficient yet flexible medium access controllers (MAC) for wireless protocols is a challenge. Not only are these protocols still evolving, they are also increasingly demanding in terms of throughput and real-time requirements. In order to support a careful application-driven architecture development, reference applications are required that expose the full system and enable the quantitative evaluation of performance-flexibility tradeoffs. For this purpose, we have captured the 802.11n MAC protocol in an executable reference application which comprises the system function and its environment including traffic scenarios. We model the reference in Click, a packet processing framework. The functionally-correct model captures performance-relevant aspects such as the wireless protocol timing exactly. Leveraging extensions to Click we can use the model for the development and deployment of embedded architectures. Our 802.11n MAC model comprises between 118 and 1238 functional elements and can be simulated in real time depending on the scenario. Due to its modularity, additional scenarios can be added productively.

A wireless network (WLAN) provides unique challenges to system design. A WLAN uses a shared and highly unreliable medium, where protocols must rely on precise timing of requests and responses to detect submission errors and priorities among network nodes. In addition, WLAN stations are often embedded and have tight constraints on power, costs, and performance. To design WLAN nodes, precise estimations on performance and resource usage are needed for the complete network system to explore the design space and assess the quality of solutions. Our SystemClick framework combines SystemC with resource models and performance annotations derived from actual implementations based on Click. Model generation is automated, and the performance of a SystemClick model is obtained depending on actual activation patterns of different functional blocks in the model. A 802.11 a/b/g/e case study demonstrates our approach for the analysis of real-time critical systems.

This paper focuses on designing network processing software for embedded processors. Our design flow CRACC represents an efficient path to implementation based on a modular application description, while avoiding much of the overhead of existing component-based techniques. We illustrate results for a real-world application implementing a full IP-based DSL Access Multiplexer (IP-DSLAM) system. We quantify overhead and optimization potential incurred by our modular implementation. We also point out how CRACC can be deployed for HW-SW partitioning and design space exploration.

We describe a modular reference implementation of an IP-based DSL access multiplexer (DSLAM). We identify deployment trends and primary tasks a future DSLAM has to offer. The implementation is representative of applications in access networks and indicative of real-world performance. To accomplish these goals our tool flow CRACC takes a modular application description and generates code for embedded processors that can easily be ported to different platforms. The derived implementation serves as a benchmark for DSLAM systems. It therefore allows the comparison of different architectures, partitioning, and mapping decisions. In addition to a full system benchmark, our reference implementation is a functionally correct realization with defined evaluation environment, traffic sources, and load scenarios. We present evaluation results of our DSLAM implementation on several embedded processors.

We identify deployment trends and primary tasks a future DSL access multiplexer (DSLAM) has to offer. We reveal two corner cases: IP-based (high-end) versus Ethernet-based (cost-optimized) access networks. We derive the need for flexible hardware platforms to support fast customization and adaptation to new protocol standards. To accomplish efficiency and ease-of-use we employ programmable multiprocessor platforms and use our tool flow CRACC that takes a modular application description and generates code for various embedded processors

Programming multi-processor ASIPs, such as network processors, remains an art due to the wide variety of architectures and due to little support for exploring different implementation alternatives. We present a study that implements an IP forwarding router application on two different network processors to better understand the main challenges in programming such multi-processor ASIPs. The goal of this study is to identify the elements central to a successful deployment of such systems based on a detailed profiling of the two architectures. Our results show that inefficient partitioning can impact the throughput by more than 30%; a better arbitration of resources increases the throughput by at least 10%, and localization of computation related to the memories can increase the available bandwidth on internal buses by a factor of two. The main observation of our study is that there is a critical lack of tools and methods that support an integrated approach to partitioning, scheduling and arbitration, and data transfer management for such system implementations.