No abstract available.

Content-based Image Retrieval (CBIR) involves retrieving images similar to an example query image in terms of some features extracted from the image. However, inherent subjectivity in user perception of an image results in retrieved images that are largely irrelevant to the user. We propose a novel methodology for efficient understanding of user perception from the query image itself. Our system automatically generates a set of modified images, after the user selects object(s) of interest from the segmented query image. Our goal is to learn the retrieval parameters by modifying the segment-level description of the query image. Segment-level description includes individual segment properties as well as the inter-segment relationships. The user perception is then learnt on the basis of user feedback on this set of modified images. We demonstrate the feasibility and advantages of the proposed approach with examples. The proposed methodology of intra-query learning saves the cost of repeated database search incurred in existing relevance feedback based approaches.

Cyclic redundancy check (CRC) is one of the most important error-detection schemes used in digital communications. A new parallel algorithm for CRC generation and its software as well as hardware implementation is described. For the software implementation, this paper has focused on the 32-bit CRC used in the Ethernet, computed on a general purpose PowerPC microprocessor with the new AltiVec technology. A speedup by a factor of 4.57 over the standard table-lookup algorithm was obtained. A hardware implementation of the algorithm is then discussed, which yields an unlimited speed-up potential over the bit-wise serial algorithm.

The AltiVec technology is a SIMD (single instruction multiple data) extension to PowerPC architecture. It is intended to provide architectural support for performance improvement of various image and signal processing applications, including speech processing, on a general-purpose processor implementation, such as, the PowerPC line of processors. We have implemented some of the common speech processing algorithms on AltiVec architecture. The algorithms discussed in this paper are autocorrelation computation, linear prediction coefficients computation via Levinson-Durbin method and Schur (1917) recursion and part of the GSM speech compression system. AltiVec obtained significant speedups on all these algorithms, compared to the scalar PowerPC implementation. We also found that additional speedup was achievable by porting to new, more SIMD-friendly algorithm.

Trace driven simulation is a common technique for evaluating different machine design options. Since the computing resources needed for simulation depend on the size of the trace, it is not always practical to use the complete trace of an application for simulation. This paper proposes a new technique, profile-driven sampling, for obtaining a reduced trace that is representative of the complete trace. Inaccuracy in the prediction of performance using such a reduced trace, is generally less than that from reduced traces using published techniques. For example, the prediction inaccuracy due to profile-driven sampling is 50 percent less than that using periodic time-based sampling. Profile-driven sampling also eliminates sensitivity to sampling parameters, such as sample size and inter-sample interval of periodic window based trace sampling, resulting, in a simple and robust trace generation process.

Recent simulation based studies suggest that while superpipelines and superscalars are equally capable of exploiting fine grained concurrency, multiprocessors are better at exploiting coarse grained parallelism. An analytical model that is more flexible and less costly in terms of run time than simulation, is proposed as a tool for analyzing the tradeoff between superpipelined processors, superscalar processors, and multiprocessors. The duality of superpipelines and superscalars is examined in detail. The performance limit for these systems has been derived and it supports the fetch bottleneck observation of previous researchers. Common characteristics of utilization curves for such systems are examined. Combined systems, such as superpipelined multiprocessors and superscalar multiprocessors, are also analyzed. The model shows that the number of pipelines (or processors) at which the maximum throughput is obtained is, as memory access time increases, increasingly sensitive to the ratio of memory access time to network access delay. Further, as a function of interiteration dependence distance, optimum throughput is shown to vary nonlinearly, whereas the corresponding optimum number of processors varies linearly. The predictions from the analytical model agree with similar results published using simulation based techniques.>

When the instruction level parallelism exceeds the available machine parallelism, a decision must be made as to which instructions get priority. This paper investigates the performance potential of five dynamic scheduling algorithms to prioritize instructions beyond basic blocks, thereby increasing processor utilization and performance. Trace-driven simulations for six benchmarks are used to analyze scheduling performance. A unique pipelining approach is introduced to address implementation limitations.>

Detecting independent operations is a prime objective for computers that are capable of issuing and executing multiple operations simultaneously. The number of instructions that are simultaneously examined for detecting those that are independent is the scope of concurrency detection. The authors present an analytical model for predicting the performance impact of varying the scope of concurrency detection as a function of available resources, such as number of pipelines in a superscalar architecture. The model developed can show where a performance bottleneck might be: insufficient resources to exploit discovered parallelism, insufficient instruction stream parallelism, or insufficient scope of concurrency detection. The cost associated with speculative execution is examined via a set of probability distributions that characterize the inherent parallelism in the instruction stream. These results were derived using traces from a Multiflow TRACE SCHEDULING compacting FORTRAN 77 and C compilers. The experiments provide misprediction delay estimates for 11 common application-level benchmarks under scope constraints, assuming speculative, out-of-order execution and run time scheduling. The throughput prediction of the analytical model is shown to be close to the measured static throughput of the compiler output.>

Introduces a technique to enhance the ability of dynamic ILP processors to exploit (speculatively executed) parallelism. Existing branch prediction mechanisms used to establish a dynamic window from which ILP can be extracted are limited in their abilities to: (i) create a large, accurate dynamic window, (ii) initiate a large number of instructions into this window in every cycle, and (iii) traverse multiple branches of the control flow graph per prediction. The authors introduce control flow prediction which uses information in the control flow graph of a program to overcome these limitations. They discuss how information present in the control flow graph can be represented using multiblocks, and conveyed to the hardware using Control Flow Tables and Control Flow Prediction Buffers. They evaluate the potential of control flow prediction on an abstract machine and on a dynamic ILP processing model. The results indicate that control flow prediction is a powerful and effective assist to the hardware in making more informed run time decisions about program control flow.>

The authors provide a common platform for modeling different schemes for reducing the branch-delay penalty in pipelined processors as well as evaluating the associated increased instruction bandwidth. Their objective is twofold: to develop a model for different approaches to the branch problem and to help select an optimal strategy after taking into account additional i-traffic generation by branch strategies. The model presented provides a flexible tool for comparing different branch strategies in terms of the reduction it offers in average branch delay and also in terms of the associated cost of wasted instruction fetches. This additional criterion turns out to be a valuable consideration in choosing between two strategies that perform almost equally. More importantly, it provides a better insight into the expected overall system performance. Simple compiler-support-based low-implementation-cost strategies can be very effective under certain conditions. An active branch prediction scheme based on loop buffers can be as competitive as a branch-target-buffer based strategy.>