The letter presents an improved algorithm for computation of general integer-order Hankel transforms, which is back-projection based. The original algorithm breaks the Hankel transform into an inverse fast Fourier transform and a discrete summation involving trigonometric terms (which is more computationally intensive). In this work, by varying the number of terms of the discrete summation with the transform order, the number of trigonometric computations and multiplications can be reduced drastically, which leads to overall computational complexity improvement. To be precise, the time complexity constant is reduced so much that our algorithm is faster than the state-of-the-art, while being O(N2). The algorithm has been simulated in MATLAB and a performance improvement of 6.04x in the discrete summation step (average case) over the original algorithm has been obtained. Finally, computational error of our proposed algorithm has been obtained, which is better than the baseline algorithm, and is comparable to the state-ofthe-art.

An Arbiter PUF (APUF) is a useful hardware security primitive. However, FPGA-based design and implementation of APUF circuits with superior values of quality metrics have proven to be extremely challenging. In this work, we have designed a novel 64-bit APUF which is "robust-by-construction", i.e., it has close to ideal values of quality metrics when implemented. The circuit structure and methodical implementation on a Xilinx FPGA platform ensure that the response bit is unbiased, and is dependent on intrinsic process variation alone. The effect of placement and routing tools and the choice of last-stage arbiters have been investigated in detail. Our implemented APUF achieves average Uniformity, Uniqueness, Steadiness, Min-Entropy, and Reliability (evaluated at four operating temperatures) metric values of 51.22%, 50.81%, 1.82%, 88.38%, and 99.34%, respectively. A software-based fuzzy error correction scheme is used on the responses generated at different temperatures. The design is also found to be strongly resistant to machine learning based model-building attacks, with Logistic Regression (LR) and Support Vector Machine (SVM) prediction accuracies of 51.22% and 52.61% respectively, on a dataset of 2,097,152 CRPs using additive delay models and a security analysis is performed using MLP modelling-attacks of the pypuf framework.

Orthogonal time frequency space (OTFS) modulation has established itself as a dependable protocol for high-speed vehicular communication. This pioneering technique operates within a novel 2-D delay-Doppler domain waveform. When compared with conventional modulation methods like orthogonal frequency-division multiplexing (OFDM), OTFS demonstrates superior performance enhancements in scenarios involving rapidly moving wireless channels. This article begins by initially unveiling the input–output association of the OTFS signal within the delay-time domain. A comprehensive comparison with the established OFDM waveform highlights the potential of OTFS for achieving a notably lower bit error rate (BER) under various conditions, which has been obtained by using the minimum mean square equalizer (MMSE) equalization technique. Finally, we have proposed a novel and low-complexity VLSI architecture for the OTFS transmitter and the receiver by using the lower–upper (LU) decomposition technique for the first time in the literature. We have compared the performance metrics of our proposed transmitter architecture with the existing work, where our design works 7.394% faster than others, utilizing 89.354% less in the number of lookup tables (LUTs) and 79.984% less in the number of flip-flops (FFs), which shows that our design is more optimized in latency and resource utilization. There is no architecture design of the OTFS receiver part in the existing literature to compare; we have shown the resource utilization of our proposed receiver architecture for the first time in the literature, followed by timing analysis and functionality testing of the proposed architecture.

The method to map the neural signals to the neuron from which it originates is spike sorting. A low-power spike sorting system is presented for a neural implant device. The spike sorter constitutes a two-step trainer module that is shared by the signal acquisition channel associated with multiple electrodes. A low-power Spiking Neural Network (SNN) module is responsible for assigning the spike class. The two-step shared supervised on-chip training module is presented for improved training accuracy for the SNN. Post implant, the relatively power-hungry training module can be activated conditionally based on a statistics-driven retraining algorithm that allows on the fly training and adaptation. A low-power analog implementation for the SNN classifier is proposed based on resistive crossbar memory exploiting its approximate computing nature. Owing to the direct mapping of SNN functionality using physical characteristics of devices, the analog mode implementation can achieve ∼21 × lower power than its fully digital counterpart. We also incorporate the effect of device variation in the training process to suppress the impact of inevitable inaccuracies in such resistive crossbar devices on the classification accuracy. A variation-aware, digitally calibrated analog front-end is also presented, which consumes less than ∼50 nW power and interfaces with the digital training module as well as the analog SNN spike sorting module. Hence, the proposed scheme is a low-power, variation-tolerant, adaptive, digitally trained, all-analog spike sorter device, applicable to implantable and wearable multichannel brain-machine interfaces.

Compressed sensing (CS) enables the reconstruction of sparse signals from a small number of linear measurements. However, sparse signal recovery algorithms require significant computational effort, even for problems of moderate size, and make their hardware realization a highly challenging task. In this paper, we present a novel architecture for the reconstruction of the sparse signal using the recently proposed Enhanced Approximate Message Passing (EAMP) algorithm. The EAMP algorithm shows better performance in terms of convergence rate and sparsity measurement trade-off as compared to AMP, IST and IHT techniques. The execution time of the proposed design has been reduced by maximizing parallelism with an appropriate level of unfolding. It receives CS measurements (y) and the number of non-zero elements (K) in the input vector from the encoder. Depending on the value of K, one sensing matrix (Φj) is selected from the code book Φ. The reconstruction algorithm (EAMP) recovers the input vector (s) by using y and Φ. Bitonic sorting has been used to identify the thresholding value in the EAMP algorithm. The proposed architecture for EAMP algorithm has been synthesized using Synopsys design compiler with 65 nm technology CMOS standard cell libraries. It occupies 719.15 KGE and consumes 315.5 mW power at a frequency of 400 MHz. It is suitable for any arbitrary sparsity-based signal restoration and CS problems.

Binary compressed sensing (BCS), in which signals of interest have binary values, finds applications in areas including fault detection and wireless sensor networks. In this article, a low-complexity VLSI architecture for BCS based on interval passing algorithm is proposed. Moreover, the algorithm is modified in order to reduce its complexity without significant loss in performance, and its corresponding VLSI architecture is proposed. Binary low-density parity check (LDPC) matrices based on finite geometry have been used as measurement matrices. The proposed VLSI architectures have been synthesized in both ASIC and field-programmable gate array (FPGA) platforms. The hardware consumption of the proposed designs is independent of sparsity values. Moreover, the proposed architectures offer high frequency of operation and low reconstruction time when compared to the state-of-the-art designs. Specifically, the 65-nm ASIC realization operates at a maximum frequency of 500 and 666.67 MHz and offer a reconstruction time of 6.3 and 4.7 ns, respectively, for a $64\times 256$ deterministic measurement matrix.

Low‐density parity‐check (LDPC) codes are predominantly used in many energy scavenging devices, data centres, and communication devices. In this work, the authors propose a high‐throughput parallel bit‐flipping (BF) decoder using multithreshold BF algorithm. The decoder is endowed with features including low interconnect complexity, simpler computations, and high throughput. The decoder has been synthesised in 65 nm technology for (273, 191) and (1023, 781) finite‐geometry LDPC (FG‐LDPC) codes. These decoders require an area of 0 . 1 and 0 . 45 mm 2 , and they achieve an average throughput of 147 . 57 and 268 . 5 Gbps and energy efficiency of 0 . 92 and 0 . 91 pJ/bit for (273, 191) and (1023, 781) FG‐LDPC codes, respectively. Compared to the state‐of‐the‐art design, the proposed designs offer 4 . 5 times higher normalised throughput.

A novel Denial-of-Service attack for Networks-on-Chip, namely illegal packet request attack (IPRA), has been proposed and measures to mitigate the same have been addressed. Hardware Trojans, which cause these attacks, are conditionally triggered inside the routers at the buffer sites associated with local core, when the core is idle. These attacks contribute to the degradation of network performance and may even create deadlocks, which can raise serious concerns in time critical systems. A security unit has been proposed to detect these attacks and mitigate the consequent loss by guiding the control units of the corresponding buffers to either isolate or mask the attacked buffers in runtime. Area and power overheads of the proposed secure router are found to be a maximum of 1.69% and 0.63% respectively when compared to a baseline router in a 16×16 Mesh network. The proposed secure router can also improve the normalized execution time as well as energy consumption of benchmark applications under considered IPRAs.

In the state‐of‐the‐art single channel speech enhancement techniques, the short‐time spectral amplitude is modified while the effect of the phase corruption due to the contamination of additive noise is neglected. This study introduces an improved speech enhancement algorithm based on a phase‐aware multi‐band spectral subtraction technique which estimates the spectral amplitude of the clean speech signal by considering the phase of the speech and noise signal components, and uses the estimated phase of the clean speech signal for signal reconstruction in the time domain. Experimental results show that the proposed algorithm yields better performance in terms of various objective and composite quality measures and other intelligibility assessment metrics while compared with other existing spectral subtraction methods. Using the composite objective measure quality evaluation technique, it is observed that the overall signal quality of the enhanced speech signal is improved on an average by 70% at 0 dB global input signal‐to‐noise ratio by using the proposed approach.

The modern digital hearing aids suffer from the problem of degradation of perceived signal quality and intelligibility of audio signal when signal to noise ratio (SNR) of the input signal becomes very low. In this work, a speech enhancement algorithm is proposed where the magnitude spectrum of clean speech is estimated by using two separate Bayesian estimators derived from two different cost functions. For the voiced regions, the perceptually motivated adaptive β-order weighted minimum mean square error (MMSE) estimator is used and the phasestructure of the voiced region is also reconstructed using a harmonic model of speech. On the other hand, for the unvoiced segments, Bayesian estimator with modified Itakura-Saito (MIS) cost function is utilized for estimating the magnitude spectrum of clean unvoiced signal. The proposed algorithm is simulated under different non-stationary noisy environments at various signal to noise ratio values. The experimental results show that the proposed speech enhancement framework performs better than other standard benchmark methods in terms of several quality and intelligibility assessment metrics of perceived audio signal.

This brief proposes a two-step optimization technique for designing a reconfigurable VLSI architecture of an interpolation filter for multistandard digital up converter (DUC) to reduce the power and area consumption. The proposed technique initially reduces the number of multiplications per input sample and additions per input sample by 83% in comparison with individual implementation of each standard's filter while designing a root-raised-cosine finite-impulse response filter for multistandard DUC for three different standards. In the next step, a 2-bit binary common subexpression (BCS)-based BCS elimination algorithm has been proposed to design an efficient constant multiplier, which is the basic element of any filter. This technique has succeeded in reducing the area and power usage by 41% and 38%, respectively, along with 36% improvement in operating frequency over a 3-bit BCS-based technique reported earlier, and can be considered more appropriate for designing the multistandard DUC.

Novel high-throughput architecture for a turbo decoder, which has been conceived by combining the advantages of pipelining and parallel processing, is proposed. Increase in throughput has been achieved by pipelining the add compare select offset (ACSO) unit and advancing the normalisation process in the ACSO unit based on global overflow protection logic. The proposed turbo decoder also benefits from incorporating low-complexity contention-free interleaver. The present work has demonstrated that a 32 maximum a posteriori probability (MAP) decoder core achieves a data rate of 1.138 Gbps at a maximum clock frequency of 486 MHz when implemented in a 90 nm process technology. Thus, the proposed turbo decoder meets the throughput requirement of modern wireless communication standards like third-generation partnership project (3GPP) long-term evolution (LTE).