The articles in this special issues are the first of two special issues that will provide an in-depth treatment of the subject of reconfigurable systems as enabled through advancements in the electrical engineering field, as well as the approaches we use to manage complexity in systems having millions of fixed and programmable elements. It is our view that the frenetic evolution of the field programmable gate array (FPGA) as a preeminent digital platform will not only continue for the foreseeable future, but will serve as an inspiration/template for other functional domains to include analog, radio-frequency, photonic, and even those not strictly electrical in nature to include thermal, fluidic, and mechanical. This issue will serve as an immersion into the subject of reconfigurable systems, both for the purposes of gaining familiarity with essential theoretical elements, the key developments in the field, and the potential future directions.

Reconfigurability can be thought of as software-defined functionality, where flexibility is controlled predominately through the specification of bit patterns. Reconfigurable systems can be as simple as a single switch, or as abstract and powerful as programmable matter. This paper considers the generalization of reconfigurable systems as an important evolving discipline, bolstered by real-world archetypes such as field programmable gate arrays and software-definable radio (platform and application, respectively). It considers what reconfigurable systems actually are, their motivation, their taxonomy, the fundamental mechanisms and architectural considerations underlying them, designing them and using them in applications. With well-known real-world instances, such as the field programmable gate array, the paper attempts to motivate an understanding of the many possible directions and implications of a new class of system which is fundamentally based on the ability to change.

The articles in this special issue focus on reconfigurable systems. Reconfigurability is about "change," specifically soft-defined change, whereby through the manipulation of bit sequences we can customize the properties of components, and in some cases define systems themselves. One can design systems for reconfigurability (the art of engineering degrees of freedom into embedded systems), so that users expecting this reconfigurability can exploit it. This issue focuses on important reconfigurable platforms [field-programmable gate arrays (FPGAs)], development tools, and applications (reconfigurable computing and software radios). As we discussed, reconfigurability can be both dynamic and adaptive, but one should not confuse the two concepts. Reconfigurability refers to specific features that can be changed (to include dynamic and partial reconfigurability), whereas adaptiveness addresses the behavioral constructs that inform how reconfigurable features might best be exploited in live use conditions.

We describe a dynamically reconfigurable image processing system that reaches real time video processing performances despite reconfiguration time overhead. The system is composed of reconfigurable pixel processing units set to process several pixels in parallel. We present a scheme for optimizing a LUT-based architecture by directly mapping it into the Xilinx FPGA CLB primitives. Internally controlled dynamic partial reconfiguration is to modify the LUT values at run-time without stalling the overall operation. The combination of optimized implementations with CLB primitives and dynamic partial reconfiguration leads to multifunctional, area-efficient, and highperformance realizations of LUT-based pixel processing systems. We present results from a dynamically reconfigurable high-performance LUT-based image/video processing system. Experimental measurements show that the system achieves speeds of 226 Mbps with small resource utilization. The architecture can dynamically reconfigure the image processing operation at each new frame and still reach real-time video processing speeds (640 times 480 graylevel frames). We also evaluate the effect that increasing partial reconfiguration rates have on the system's overall performance.